- Lockheed Martin (Sunnyvale, CA)
- Description Join Our Team as a ASIC/ FPGA Verification Engineer where you will work on the development of a sophisticated state‑of‑the‑art avionics product in ... are seeking a highly talented and motivated ASIC & FPGA Verification Engineer who has...ASIC/ FPGA verification experience with modern verification methodologies such as UVM , OVM or… more
- Lockheed Martin (Sunnyvale, CA)
- A global aerospace and defense company seeks an ASIC/ FPGA Verification Engineer in Sunnyvale, CA. You'll work on cutting-edge avionics products in a team ... focused on ASIC/ FPGA design and verification . Required qualifications include...include a Bachelor's in Electrical Engineering, experience with modern verification methodologies such as UVM , and 3+… more
- SQL Pager LLC (Sunnyvale, CA)
- … methodologies and flows * Hand-on experience: System Verilog, C++, Perl/Python, UVM , Synthesis, Formal Verification , Static Timing Analysis * Experience with ... computing architecture * Participating in Architecture definition and modeling, verification test plan and testbench. * Developing the micro-architecture… more
- Compunnel, Inc. (Mountain View, CA)
- A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced ... methodologies and requires strong expertise in SystemVerilog, UVM , and debugging skills. The ideal candidate will develop verification plans, utilize… more
- SQL Pager LLC (San Jose, CA)
- A leading company in semiconductor technology is seeking a VLSI Verification Engineer who will collaborate with design teams and develop verification ... environments. The ideal candidate has a strong background in ASIC/ FPGA verification , advanced knowledge of System Verilog, and is skilled in both C/C++ and… more
- Compunnel, Inc. (Mountain View, CA)
- The FPGA Verification Engineer will be responsible for verifying FPGA designs using advanced methodologies and tools. This role requires strong expertise ... deliverables. Key Responsibilities Develop and execute verification plans for FPGA designs using SystemVerilog and UVM methodology. Utilize industry-standard… more
- Compunnel, Inc. (Santa Clara, CA)
- We are seeking a highly motivated and skilled FPGA Verification Engineer to join our team. This role is responsible for verifying complex FPGA designs to ... Engineering, or related field. 3+ years of experience in FPGA verification . Strong understanding of FPGA... design principles and architectures. Proficiency in SystemVerilog and UVM . Experience with verification tools such as… more
- Apple Inc. (Cupertino, CA)
- …power testing on the emulation platform, and develop code for design and verification using Verilog, SystemVerilog, and UVM . Additionally, you will develop ... writing synthesizable SystemVerilog/Verilog code and assertions. Experience with SystemVerilog verification environments including C/C++ DPI and UVM . Experience… more
- Advanced Micro Devices (San Jose, CA)
- …collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role As a verification engineer in the AECG Group, you will help bring to life ... cutting-edge FPGA , ASICs for variety of target customers. As a...software driver use cases Code IP or SS level UVM based testbenches, verification components - monitors,… more
- SQL Pager LLC (San Jose, CA)
- …years or MSEE with 1+ years experience Advanced knowledge of standard ASIC/ FPGA verification flows including simulation, testbench development, and post silicon ... and understand specifications / architectures / micro-architectures Define and review verification test plans Develop block level and chip level verification… more
- Apple Inc. (Santa Clara, CA)
- …Clock Control verification . Description As a CPU Processor Power Management Verification Engineer , you will have the responsibilities as follows: Work ... on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of...in design verification environments like random constraint verification and/or UVM base testbenches Experience in… more
- Analog Group (San Jose, CA)
- …and network equipment. Job Function: Digital Design (RTL design): ASIC or FPGA from concept to implementation. Digital Verification : Development test plans, ... The Sr. Digital Design Engineer candidate must have demonstrated success in digital...target schedule. Qualifications: 3-5 years' experience in design plus verification of ASIC or FPGA . Strong knowledge… more
- Qualcomm (Santa Clara, CA)
- …of the synthesized FPGA RTL. System level RTL simulation & design verification . Support chip bring up and post silicon debug. Debug functional and timing models. ... from RTL. 4+ years of hands‑on emulator platforms, platform bringup, digital design, verification , debugging, and waveform viewers. 4+ FPGA systems based on… more
- Mythic, Inc. (Palo Alto, CA)
- …(Karnataka, India). About This Role We are seeking a Director / Principal Engineer of Digital Design Verification to provide technical and strategic leadership ... boot, security, clocking, reset, and DFT features. Define and enforce UVM -based verification methodologies. Drive adoption of: Coverage-driven verification… more
- FLIR Systems, Inc. (Milpitas, CA)
- …optimization. + Integrate PCIe IP cores, DMA engines, and custom protocol decoders.* ** Verification & Debug** + Build SystemVerilog/ UVM testbenches for block and ... Staff Logic Design Engineer page is loaded## Staff Logic Design Engineerlocations:...for protocol capture, analysis, and emulation. You'll work on FPGA -based systems that decode and analyze High speed protocols… more
- Cisco (Milpitas, CA)
- …leading FPGA devices and tools. **Preferred Qualifications** + Experience with UVM and/or VMM Verification methodology. + Experience with high-speed design ... networking system requirements, mapping them into functional blocks for FPGA implementation, working with the cross functional team to...ASR8000 routers. You will be a member of the FPGA team that designs control path FPGAs for the… more
- Microsoft Corporation (Mountain View, CA)
- …manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join our team! **Responsibilities** + Perform pre-silicon ... verification for complex IP, including creating testplans, developing Universal Verification Methodology ( UVM ) components and environments from scratch,… more
- Broadcom (San Jose, CA)
- …verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM ); designing verification ... flows and DV methodologies + Strong working knowledge of object oriented verification languages (OVM, UVM , etc.), C/C++, Perl, and scripting skills. +… more
- SpaceX (Sunnyvale, CA)
- Principal Design Verification Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're...Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC and/or FPGA verification at block and system level… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... verification methods + Experience in RTL design for FPGA or emulation + Experience in Assembly, startup code...with test plan definition + Substantial background in creating UVM Test Benches, developing tests, and debugging designs +… more
