- Cerebras (Sunnyvale, CA)
- …over 10 times faster than GPU-based hyperscale cloud inference services. About The Role As a lead front-end design engineer , you will be a key part of the ... Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient,… more
- Cerebras (Sunnyvale, CA)
- A leading AI hardware company in California seeks a lead front-end design engineer to spearhead the next generation of its groundbreaking Wafer Scale Engine. ... The ideal candidate will possess 10+ years of RTL design experience and a master's degree, with skills in high-performance computing and collaboration with… more
- SQL Pager LLC (Sunnyvale, CA)
- …Required Skills * MS with 10+ years or PhD with 8+ years, 5+ years in ASIC design team lead . * Experience in logic design on high-performance data center ... verification test plan and testbench. * Developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals. * Bring up the… more
- Meta (Sunnyvale, CA)
- …emulation and prototyping models on industry-standard emulation and prototyping platforms Design , build, and execute comprehensive emulation test plans to ensure ... model accuracy and support pre-silicon validation efforts Lead the development and adoption of best-in-class emulation methodologies to accelerate hardware… more
- Synopsys, Inc. (Sunnyvale, CA)
- …the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design , verification, and IP integration, empowering the creation ... Technical: Proficiency in Linux environment Good knowledge of digital electronics and RTL (Verilog) Good knowledge of C/C++, and Python (or another scripting… more
- Advanced Micro Devices (Santa Clara, CA)
- …The ideal candidate will have a proven track record in creating scalable digital microarchitectures and will work closely with various teams to ensure the successful ... delivery of complex SoCs. Candidates must possess excellent leadership, communication, and collaboration skills. A background in computer engineering or electrical engineering is preferred. #J-18808-Ljbffr more
- Advanced Micro Devices (Santa Clara, CA)
- …AMD. KEY RESPONSIBILITIES Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, ... In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the … more
- Intel Corporation (Santa Clara, CA)
- …seeking a Senior Design Engineer - AI SoC Development in California to lead logic design and RTL coding for cutting-edge AI applications. The ideal ... candidate will have over 7 years of experience in ASIC/SoC development, strong technical skills, and a collaborative mindset. Responsibilities include defining architecture, optimizing designs for performance and power, and mentoring junior engineers. This… more
- Upscaleai (Santa Clara, CA)
- …define and document micro-architecture on next generation designs. Responsible for the logic design / RTL entry and timing closure in a high-performance custom CPU ... and/or logic Core. Interface with physical design , design for test, power, and performance...to diverse and inclusive teams. Able to thrive or lead in a fast-paced startup environment. Preferred: 8+ years… more
- Intel Corporation (Santa Clara, CA)
- # **Welcome!**## .Senior Design Engineer - AI SoC Development page is loaded## Senior Design Engineer - AI SoC Developmentlocations: US, California, ... Computer Engineering, or Computer Science* 7+ years of experience in RTL design and implementation for ASIC/SoC development**Preferred Qualifications** *… more
- Cadence Design Systems (San Jose, CA)
- Lead Applications Engineer DDR Design IP page is loaded## Lead Applications Engineer DDR Design IPlocations: SAN JOSEtime type: Full timeposted ... matter where you are in your career. As a Lead Technical Presales Engineer , you will use...definers and designers Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts… more
- Analog Group (San Jose, CA)
- The Sr. Digital Design Engineer candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. ... Other key skills include technical/project leadership, documentation, RTL design knowledge, backend flow and tools...flow and tools knowledge. Candidate will be expected to lead designer, verification, and be technical focus on one… more
- Credo Semiconductor, Inc. (San Jose, CA)
- …technologies - because at Credo, We Connect. About the Role As a Senior Physical Design Engineer , you will manage all aspects of physical design and ... PD/integration teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block-level physical implementation from … more
- Encore Semi Llc (San Jose, CA)
- Sr Physical Design Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. Remote (Anywhere ... in US) Responsibilities Lead full-chip and block-level physical design for...routing of critical paths. Establish, improve, and scale physical design methodologies, automation, and RTL -to-GDS flows. Provide… more
- Cadence Design Systems (San Jose, CA)
- Senior Principal Emulation Design Engineer page is loaded## Senior Principal Emulation Design Engineerlocations: SAN JOSEtime type: Full timeposted on: ... on the world of technology.**We are seeking a highly skilled** Design Engineer ** to join our Palladium Solutions...configuration, control and status monitoring.** + **SystemVerilog** for synthesizable RTL design + **C and Python** for… more
- nEye Systems, Inc. (Santa Clara, CA)
- …performance, efficiency, and scalability. Role Overview We're seeking a Lead Hardware Engineer to drive the design and development of advanced digital and ... of lab debug tools (oscilloscopes, logic/protocol analyzers). Familiarity with FPGA design flow ( RTL coding, synthesis, verification) and integration. Excellent… more
- Ll Oefentherapie (Santa Clara, CA)
- …dedicated Senior Principal Engineer to run security architecture within a hardware design organization and to develop, implement, and own the hardware design ... and debugging firmware. FPGA implementation experience. Use of FPGAs in a hardware design context, and/or RTL /gateware implementation. #LI-SM18 #J-18808-Ljbffr more
- Advanced Micro Devices (Santa Clara, CA)
- …Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL , physical design ). Analysis and modeling: ... enhance power analysis efficiency. Collaboration: Working with other teams, including RTL , Architecture, Physical Design , Emulation, software, firmware to ensure… more
- Altera (San Jose, CA)
- …Details:** ## **Job Description: Job Summary:**Altera is seeking a passionate and driven engineer to join our Design Automation team, focusing on developing and ... clock tree synthesis (CTS), routing, and signoff.* Develop and maintain end-to-end design automation flows for RTL -to-GDSII implementation.* Create and optimize… more
- Renesas Electronics Corporation (San Jose, CA)
- …MCU, peripheral IP, volatile/non-volatile memory IP selection, partitioning of hardware/firmware, RTL design , verification, FPGA prototyping, DFT, and IC ... on-chip bus system, DMA and interrupt system Digital IP RTL design , simulation, and release Independently handle...Python, etc. Firmware development experience Language fluency in Mandarin Design Lead or Project Lead … more
