- Meta (Sunnyvale, CA)
- …performance test planning, execution, and closure Experience with compute and/or memory subsystem and/or collective performance verification Familiarity ... Summary Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design… more
- Apple Inc. (Santa Clara, CA)
- A leading technology company is seeking a CPU Performance Modeling Engineer in Santa Clara, California. This role involves optimizing CPU and cache ... micro-architecture and addressing performance bottlenecks. Candidates should have knowledge of CPU architecture and strong programming skills in C/C++. The base pay… more
- Samsung Electronics GmbH (Mountain View, CA)
- Senior Engineer , SoC Architect - Memory Subsystem Senior Engineer , SoC Architect - Memory Subsystem Job Location Mountain View, CA Job Category ... Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem , multimedia subsystems and key IP blocks for future… more
- NVIDIA Corporation (Santa Clara, CA)
- …is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a ... Senior Memory System Engineer page is loaded##...Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance , power, function and RAS in memory … more
- Cadence Design Systems (San Jose, CA)
- Sr Principal Product Engineer - Memory IP page is loaded## Sr Principal Product Engineer - Memory IPlocations: SAN JOSEtime type: Full timeposted on: ... experienced team focused on the development and support of high- performance IP related to memory protocols such...impact in our world.We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up,… more
- NVIDIA Corporation (Santa Clara, CA)
- …looking for curious, collaborative, and motivated hardware engineers to take our GPU memory subsystem from first silicon power-on to production.**What you'll be ... System Products Memory Solutions Engineer page is loaded...NVIDIA is an industry leader with groundbreaking developments in High- Performance Computing, Artificial Intelligence and Visualization. The GPU, our… more
- Apple Inc. (Santa Clara, CA)
- …Description As a CPU Performance Modeling Engineer with a focus on the memory subsystem , you will be part of a team that is defining and optimizing CPU ... CPU Performance Modeling Engineer - Platform Architecture...techniques or other aspects of CPU memory subsystem (ie prefetching, caching policies) Familiarity with performance… more
- Apple Inc. (Santa Clara, CA)
- …the cache subsystem . Minimum Qualifications In-depth knowledge of memory subsystem Academic experience with RTL/micro-architecture development Good ... the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache… more
- Clutch Canada (Mountain View, CA)
- …software and hardware. Experience with Arm ISA or other modern ISAs, SoC subsystem like interconnects, memory controllers and DMAs. Demonstrated ability to learn ... safe decisions. Role Overview: We are seeking a software engineer to focus on algorithm development for point cloud...software. This role will focus on driving CPU and memory optimizations across our LiDAR data path, ensuring efficient… more
- Renesas Electronics Corporation (San Jose, CA)
- …Chip architecture, design, and integration: MCU and peripherals, embedded flash and SRAM memory subsystem , on-chip bus system, DMA and interrupt system Digital ... Description This is an opportunity to join Renesas Infrastructure and Mixed-Signal Division, Memory Interface Product Line. You will join the team to develop the… more
- Cadence Design Systems (San Jose, CA)
- …and verbal/written communication skills is a must**Nice to have**: Experience on memory subsystem verification and/or performance analysis Knowledge of ... Engineer , you will use your knowledge of different memory interface standards to architect memory solutions...Sales staff, marketing and R&D teams to win opportunities Performance evaluations of Cadence memory IP and… more
- Cadence Design Systems (San Jose, CA)
- …protocols - DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6 * Perl/Python Scripts * Experience on memory subsystem verification and/or performance analysis * Strong ... Senior Applications Engineer - DDR Design IP page is loaded##...senior roles, you will use your knowledge of different memory interface standards to architect memory solutions… more
- Apple Inc. (Santa Clara, CA)
- …memory or highly interconnected system architectures.- RTL/micro-architecture.- Knowledge of high- performance memory subsystem , including dram controller, ... architectures from DRAM up. Explore architecture and feature trade-offs in system performance , area, and power consumption. Develop memory hierarchies for high… more
- Redwire Space (San Jose, CA)
- …Security Space. Summary We are seeking a Contractor- Sr. Principal Embedded Software Engineer for an initial period of 6 months, with the possibility of extension ... to propose and develop software solution(s) to meet system specifications including performance requirements. Work with the team to author / conduct software static… more
- Intel Corporation (Santa Clara, CA)
- # **Welcome!**## .Senior Design Engineer - AI SoC Development page is loaded## Senior Design Engineer - AI SoC Developmentlocations: US, California, Folsom: US, ... devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives...to write RTL and optimize logic to meet power, performance , area, and timing goals while ensuring design integrity… more
- Google Inc. (Mountain View, CA)
- …code developed by other developers to ensure strict adherence to real‑time performance constraints, memory optimization in embedded Linux environments, and ... Senior Software Engineer , Audio, Google Beam Location: San Francisco, CA,...with software design and architecture. Experience with real‑time audio subsystem design, implementation, or validation. Experience working with embedded… more
- nio (San Jose, CA)
- …includes optimizing latency and throughput, refining vIRQ handling, improving cache and memory subsystem efficiency (SMMU, coherency, and paging), and leveraging ... the Position**This role is ideal for an experienced **kernel** **or** **hypervisor** ** engineer ** who wants to work hands-on with the foundations of NIO's in-vehicle… more
- Arm Limited (San Jose, CA)
- …architecture integrating Arm IP and high-speed I/O subsystems to meet compute, memory , and interconnect performance targets. Partner with software, firmware, and ... Strong knowledge in areas such as heterogeneous compute, PCIe/CXL/UA Link subsystem design, security, caching, memory systems. Demonstrated communication and… more
- Mythic, Inc. (Palo Alto, CA)
- … subsystem -, and SoC-level verification plans. Lead verification of: High- performance interconnects (AXI, NoC, PCIe, CXL, UCIe); Compute pipelines (CPU, DSP, ... ACE (TM) ) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at...This Role We are seeking a Director / Principal Engineer of Digital Design Verification to provide technical and… more
- 1x.tech (Palo Alto, CA)
- …how you might contribute to our journey. Role Overview As Senior Systems Software Engineer for Vision, you will design, develop, and optimize the vision subsystem ... will help enable perception, autonomy, and teleoperation at scale, ensuring performance , responsiveness, and robustness for robots operating in diverse environments.… more
