- Qualcomm (Santa Clara, CA)
- …ASIC Design Verification Engineer with strong CPU, ASIC design and verification fundamentals to work in Qualcomm's Global SOC team. This position offers ... for the future. **The JOB** + As a member of the Global SOC Lower Power verification team, you will be responsible for verifying the ASIC low power design,… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, to firmware, and algorithms.We are seeking an SoC Modeling ASIC Engineer to support C++/Python modeling and software ... and mapping software pipelines to the dedicated hardware accelerators. **Required Skills:** SoC Modeling ASIC Engineer Responsibilities: 1. Analyze the software… more
- SpaceX (Sunnyvale, CA)
- SOC /ASIC Synthesis & Front-End STA Engineer ...with power intent and upf development for block and SOC top + Familiar with formal verification ... the ultimate goal of enabling human life on Mars. SOC /ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...IPs into RTL + Develop/modify/run RTL logic synthesis, formal verification , power intent verification and post synthesis… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking to hire a senior verification architect to design verification methodology for our next generation SOCs with AI capabilities for ... and next generation SoCs. + Design and implement new verification methodology solutions, including TB architecture, test...engineer with a real passion for improving design verification efficiency and pushing barriers? If so, we want… more
- Amazon (Sunnyvale, CA)
- …STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners, Synthesis, Place & Route ... Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our...& Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …place&route and signoff) and/or experience with functional and formal verification tools/ methodology , VIP. Understanding of semiconductor manufacturing ... technology requirements in the digital , custom and function verification space, coordination of sales strategies and efforts across...in sales and account management or as a Applications Engineer or Design Engineer with proven track… more
- Meta (Sunnyvale, CA)
- …in support of our industry leading virtual and augmented reality systems.As a Design Verification Engineer (DVEs), you will be a key contributor in planning, ... industry leading virtual and augmented reality systems. **Required Skills:** Design Verification Engineer Responsibilities: 1. Self sufficient and detail… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The team develops and ... supports static RTL verification methodologies for RTL Lint and Logical Equivalence. As...limits of technology and performance for GPU, CPU and SoC markets. What you'll be doing: + Evaluate new… more
- Microsoft Corporation (Mountain View, CA)
- …in an extremely efficient manner. We are looking for a **Principal Design Verification Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... with 3 rd party IP vendors. + Experience with IP/ SOC verification for a full product cycle... and debug principles, test benches, System Verilog, Universal Verification Methodology (UVM) and C based test… more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Microsoft Corporation (Mountain View, CA)
- …and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). + Analyse and debug test failures ... coverage for stimulus and corner cases. + Develop, audit & execute the IP/Subsystem SoC level verification plan. + Close coverage to plug verification … more
- Microsoft Corporation (Mountain View, CA)
- …clients, and augmented reality. We are looking for a **Senior Design Verification Engineer ** to work on leading-edge Intellectual Property (IP) development ... and assertions to verify design correctness. + Develop Universal Verification Methodology (UVM) components to interface between...of experience in design verification with full verification cycle on complex System On Chip ( SOC… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Verification Engineer for our Tegra group! NVIDIA is seeking outstanding Senior Verification Engineers to verify the design ... writing UVM testbench from scratch and applying constraint random methodology in UVM test environment. + Highly proficient in...Stand Out From The Crowd: + UVM knowledge and SOC verification experience. + Ambitious and highly… more
- Cisco (San Jose, CA)
- …You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification ... Who You Are * You are an ASIC Design Verification Engineer with 5+ years of related... verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...plans based on the Architecture and Micro-architecture. + Develop Verification Methodology , ensuring scalability and portability across… more
- Siemens Digital Industries Software (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based on ... who like to interact with and influence others, possess strong design and/or verification background, requiring both in depth knowledge of HDL and HVL, as well… more
- Siemens Digital Industries Software (Fremont, CA)
- …across a range of areas from application engineering support and management, verification and validation of complex semiconductor ICs, system testing, and beyond? If ... expect competent leadership from our managers and executives. This Applications Engineer (AE) position delivers technical expertise for Advance Functional … more