- Cadence Design Systems, Inc. (San Jose, CA)
- …are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain insertion, ... of professional experience in SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT insertion flows +… more
- SpaceX (Sunnyvale, CA)
- …extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr. SOC/ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA...leveraging Siemens Tessent tools + Integration and verification of Design for Test ( DFT ) IPs and fabrics… more
- NVIDIA (Santa Clara, CA)
- …with 5+ years, MSEE with 3+ years, or PhD with 2+ years of experience in DFT , system architecture, or RTL design . + Understanding of fundamental DFT topics, ... Excellent understanding of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe… more
- NVIDIA (Santa Clara, CA)
- …imagination and intelligence. Make the choice to join us today. Design -for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative ... solutions for DFT architecture, verification and post-silicon validation on some of...exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power, to ensure we are… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... formal verification using JasperGold is a plus. + Deep expertise in DFT design , methodology, and implementation. + Familiarity with related domains such as… more
- General Motors (Sunnyvale, CA)
- …the role, it can be either _Warren, MI or Sunnyvale, CA as directe_ d. ** Design for Manufacturing, Testing, Tooling Engineer ** **The Role:** General Motors is at ... internal and external customers. **Responsibilities of the Design for Manufacturing, Design for Testing, Tooling Engineer include:** + Work with cross… more
- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer ... Engineer , you will collaborate with RTL, Design for Testing ( DFT ), Floorplan, and full-chip Signoff ... practical experience. + 7 years of experience with physical design (eg from RTL to GDSII, including key stages...flows (eg, LEC, PI/SI, DRC/LVS, etc.). + Understanding of DFT including Scan, MBIST and LBIST. + Understanding of… more
- General Motors (Mountain View, CA)
- … design and development of our vehicle displays hardware. In this role, the Senior Hardware Design Engineer - Display Development will be responsible for ... for manufacturing (DFM), design for assembly (DFA), and design for testing ( DFT ) + Drive the validation and testing of hardware components and systems,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... expectations. + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/ DFT /LEC/STA) + Partner and work with back-end team until… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... to see: + MS/Phd in Electrical Engineering or Computer Engineer or related degree (or equivalent experience). + 5+...plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds to build cutting-edge ... that power everything from AI to gaming! As a Senior SOC Design Engineer , you'll...partnering with experts in ASIC design , Physical design , CAD, Package Design , Software, DFT… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering,...or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing… more
- Microsoft Corporation (Mountain View, CA)
- …solutions, automation, and quality assurance checks across front-end areas like RTL & VIP Design , Design Verification, Validation, DFT , Emulation, Design ... within Microsoft by developing workflows and software for our design engineers so that they can deliver cutting-edge silicon...can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting ... synthesis and verification, knowledge of Place and Route, and understanding of Design -for-test ( DFT ) is a plus. + Proficiency in scripting language, such as,… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic ... What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at...hands-on debugging capability and problem-solving skills. + Background in DFT timing closure for various modes eg scan shift… more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Engineer . NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's ... is required. + Understanding of ASIC design flow including RTL design , verification, logic synthesis, prototyping, DFT , timing analysis, floor-planning, ECO,… more
- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and ... CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in end-to-end cycle of… more
- SpaceX (Sunnyvale, CA)
- …extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA...planning, bus routing, sequential pipeline planning and top level design for testability ( DFT ) planning + Collaborate… more
- NVIDIA (Santa Clara, CA)
- …preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT , and ECO. + Strong communication and interpersonal skills ... As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical... Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches,… more
- NVIDIA (Santa Clara, CA)
- …make a lasting impact on the world. We are now looking for a motivated Senior Timing Closure Engineer to join our dynamic and growing Circuit Solutions Group! ... What you'll be doing: + Participate in groundbreaking processor design in deep submicron technologies. + Work as part...timing closure strategy, timing constraints, timing and power convergence, DFT , as well as ECO implementation. What we need… more