- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive DFT/ Test timing for innovative GPUs, CPUs, and SoCs at cluster level and/or ... full chip level + Work on all aspects of DFT/ Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation What… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... balance between frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT/ Test timing such as timing constraints, timing analysis, … more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …(LCLS) Engineering Division at the SLAC National Accelerator Laboratory seeks a mechanical engineer to lead the Lasers and Timing Systems Engineering Department. ... Laser and Timing Systems Engineering Department Head Job ID 5857...perspective, the department supplies engineering support to design and test proof of principal capabilities and works closely with… more
- Silicon Valley Power (Santa Clara, CA)
- …not meet the Education minimum qualifications for this position. 02 Please indicate which Senior Engineer (Civil) position you are interested in applying for. + ... ** Senior Civil Engineer ** Print (https://www.governmentjobs.com/careers/cityofsantaclaraca/jobs/newprint/4420027) ...traffic control devices. + Develop and review traffic signal timing parameters and coordination timing plans; +… more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We ... is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Physical Design Engineer ** to work on leading edge Intellectual Property ... in RTL-to-PD, but also floorplanning, place-and-route, and signoff for timing , Electro Migration and Voltage Drop (EMVD), and physical...will be needed to coordinate with RTL, Design for Test (DFT) Computer Aided Design (CAD) and SoC physical… more
- Qualcomm (San Jose, CA)
- …ATPG, coverage analysis, Transition delay test coverage analysis + Expertise in test mode timing constraints definition, knowledge in providing timing ... for the implementation and verification of DFT/DFD (Design for Test /Design for Debug) techniques for low power, multi voltage...STA constraints and work with STA team to resolve timing violations + owns IDDQ constraints generation and validation… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working ... micro-architecture and design including RTL design, synthesis, functional verification, and timing analysis using groundbreaking CAD tools and using the latest… more
- The Boeing Company (Mountain View, CA)
- …opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** at Lead, Senior & Principal levels to join us as part of our Boeing Electronic ... Surveillance and Mobility; and Autonomous Systems). As an ASIC/FPGA Engineer on the Boeing Electronic Products team you will...team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to ... micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and using the latest… more
- TrustPoint (Mountain View, CA)
- …anti-jam capabilities. The improvements will support US Government position and timing service resiliency as well as enable next-generation commercial applications ... with our microsatellite based commercial infrastructure and innovative positioning and timing services. The Position With locations outside Washington DC and in… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...automated tools. + Create prototypes of patentable ideas on test chips and drive them to be deployed across… more
- BAE Systems (San Jose, CA)
- …be a part of? Come build your career with BAE Systems. We are seeking a very senior level engineer to: + Design and RTL coding of high-speed digital circuits on ... Other incentives may be available based on position level and/or job specifics. ** Senior Principal ASIC Design Engineer (Hybrid)** **95186BR** EEO Career Site… more
- SpaceX (Sunnyvale, CA)
- …full chip and block constraint partitioning + Develop block and full chip level timing constraints for test modes. + Timing closure ownership throughout ... partitioning and timing closure in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …make an impact on the world of technology. Looking for Lead SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). Ability to lead from DFT ... and experience in scan chain insertion, compression scan technologies, memory built-in self- test (MBIST) and automatic test pattern generation (ATPG) is required… more
- NVIDIA (Santa Clara, CA)
- … Test Equipment (ATE) + Lead multi-functional efforts with DFx, Design, Timing , Test , Foundry to root-cause complicated technical problems + Find creative ... latest architecture designs to market. + Identify and implement test processes to improve manufacturing efficiency for our latest...are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Mixed-Signal/Analog/IO Circuit Design Engineer - someone who is excited to join a rapidly growing team of creative circuit design ... and Latch-Up requirements + Possess an understanding of system-level timing budgets, specs, and analysis + Working Knowledge of...plus + Hands-on experience of silicon debug with Lab test and measurement equipment is a plus + A… more
- NVIDIA (Santa Clara, CA)
- …knowledgeable in DFT, digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... Stand Out From The Crowd: + DFT experience specifically in system test features for in field test . + Bringup experience with GPU/SOC architecture is a plus. +… more
- NVIDIA (Santa Clara, CA)
- …solutions and detailed transistor-level analysis. + Create prototypes of patentable ideas on test chips and drive them to be deployed across the entire line of ... + Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required. + Basic understanding and experience working with… more
- Vector Atomic (Pleasanton, CA)
- …is building quantum devices for applications including GPS-free navigation and timing , geophysical exploration, and telecommunications. We are focused on delivering ... devices. + Experience with Linux device drivers. + Comfortable using test and measurement equipment to confirm coding performance. This includes oscilloscopes,… more