- Apple Inc. (Santa Clara, CA)
- A leading technology company in Santa Clara seeks candidates experienced in ASIC design and high-performance memory subsystems. The ideal candidate should ... of 3 years of experience. Responsibilities include driving new memory system architectures and developing performance/power simulations. Competitive compensation… more
- Amazon (San Francisco, CA)
- Sr. ASIC Design Engineer , Cloud-Scale Machine Learning Acceleration team Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure ... rapid integration of emergent technologies. We're looking for an ASIC Design Engineer to help...attributes "Learn and Be Curious" mindset. Familiarity with accelerator design , interconnects, DMAs, memory sub‑systems, CPU cores,… more
- Apple Inc. (Santa Clara, CA)
- …of the cache subsystem. Minimum Qualifications 10 + years of full time ASIC design experience in: Memory system development PPA (performance/power/area) ... and controller which is part and parcel of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system… more
- Hewlett Packard Enterprise Development LP (San Jose, CA)
- ASIC Engineer Sr StaffThis role has...& Experience: 10+ years of hands-on DFT experience in ASIC design , preferably in networking or high-speed ... cutting-edge ASICs for next-generation networking platforms. We are looking for a seasoned** Design -for-Test (DFT) Engineer ** to join our team and contribute to… more
- Cadence Design Systems (San Jose, CA)
- Lead Applications Engineer DDR Design IP page is loaded## Lead Applications Engineer DDR Design IPlocations: SAN JOSEtime type: Full timeposted on: ... Technical Presales Engineer , you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence… more
- Cadence Design Systems (San Jose, CA)
- Senior Applications Engineer - DDR Design IP page is loaded## Senior Applications Engineer - DDR Design IPlocations: SAN JOSEtime type: Full timeposted ... an impact on the world of technology.** Senior Applications Engineer - DDR Design IP Job Location:...subsystem verification and/or performance analysis * Strong knowledge of ASIC flow, RTL design in Verilog, System… more
- Cadence Design Systems (San Jose, CA)
- …innovators who want to make an impact on the world of technology.**We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ... Verilog testbenches.Requirements;US citizenship preferred.* Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for… more
- FLIR Systems, Inc. (Milpitas, CA)
- Staff Logic Design Engineer page is loaded## Staff...a plus* **7+ years** of experience in digital logic design for FPGA or ASIC .* Strong proficiency ... storage, and networking.**Role Overview**We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience,… more
- Qualcomm (San Diego, CA)
- …to help create a smarter, connected future for all. As a Qualcomm GPU ASIC Engineer , you may architect, design , implement, verify, and/or optimize ... degree in Science, Engineering, or related field and 6+ years of ASIC design , verification, validation, integration, or related work experience. Master's… more
- Medium (San Jose, CA)
- …architectures. Partition designs and justify tradeoffs across HW/FW/SW; collaborate with ASIC /SoC, digital design , verification, board, and systems teams. Bring ... development of firmware across multi‑processor embedded subsystems integrated into ASIC /SoC platforms. Partition functionality across hardware, firmware, and software;… more
- NVIDIA Corporation (Santa Clara, CA)
- …Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software ... Senior Architecture Energy Modeling Engineer page is loaded## Senior Architecture Energy Modeling...interest in energy-efficient GPU designs.* Familiarity with Verilog and ASIC design principles is a plus.* Ability… more
- Apple Inc. (Sunnyvale, CA)
- …protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you\'ll be at the center ... of the verification effort within our silicon design group responsible for crafting and productizing state of...systems, Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot… more
- Cadence Design Systems (San Jose, CA)
- …and enable the products. We are now looking for a hands-on system integration engineer who wants to expand his/her scope, work with the interactions of a complex ... function to bridge and gate-keep the full integration, validation, and characterization of ASIC , HW/PCB, SW, FW, and FPGA subsystems in the whole development cycle.… more
- Conductor (San Jose, CA)
- San Jose, California, United States Overview The ACD Design verification team independently verifies the ASIC designs against standardspecifications. This gives ... an unbiased view of ASICs as compared to the design engineers. This helps the designs to stick to...for great customer experiences. You will get involved in ASIC verification of the designs targeted for the wearables… more
- Apple Inc. (San Diego, CA)
- …of Apple device users. Our team is looking for an experienced software engineer with modern embedded C++ and Python skills and experienced in software‑defined‑radio ... system running on a heterogeneous computing system (CPU+FPGA, CPU+GPU, CPU+ ASIC accelerator, etc). Strong familiarity with low‑level systems programming using… more
- Apple Inc. (San Diego, CA)
- …of Apple device users.Our team is looking for an experienced software engineer with modern embedded C++ and Python skills and experienced in software-defined-radio ... system running on a heterogeneous computing system (CPU+FPGA, CPU+GPU, CPU+ ASIC accelerator, etc). Strong familiarity with low-level systems programming using… more
- Qualcomm (San Diego, CA)
- …interface enablement, multicore scheduler boot, next‑gen volatile (DDR) and non‑volatile memory (UFS, NVMe, eMMC, NAND, SPI‑NOR) and interface (USB, PCIe) ... initialization, and device driver development. Responsibilities Design , develop and integrate SoC firmware features, diagnostics and test capabilities for QCT boot… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of ... + BS, MS, or PhD in Electrical Engineering, Computer Engineer , or related degree required (or equivalent experience) +...3+ years of relevant and proven ASIC design experience and a background in DRAM memory… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll ... you'll be doing: + As a member of our Memory Subsystem Design team, you will collaborate...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT,… more
- Northrop Grumman (Jessup, MD)
- …reality and deliver remarkable new advantages to the warfighter. We are seeking a front-end ASIC design engineer for design and verification of ... level. Qualifications for both are listed below:** **Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:** + Bachelor's degree in… more
