- Google (Sunnyvale, CA)
- …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
- Qualcomm (San Diego, CA)
- …**General Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing the next generation ... - Apply computer architecture and optimization techniques for improving power , performance, and area of the IPs - Assist...- Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT, synthesis, FV,… more
- Google (Sunnyvale, CA)
- …experience with System Level Test or System validation. + Experience with ASIC or SoC prototype bring-up, debug, functional verification, or functional manufacturing ... process, Kernel, and CPU performance. + Experience implementing secure ASIC /SoC manufacturing solutions (provisioning, e-fuse programming, or life-cycle management).… more
- Qualcomm (Santa Clara, CA)
- …of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such ... model development and formal verification (property checking). Learn and deploy power -aware UPF verification flow and methodology. Involve in developing automation… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... Computer Architecture and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis,… more
- NVIDIA (Santa Clara, CA)
- …Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering teams. This position ... of relevant industry experience + Exposure to computer architecture, ASIC design, and verification methodology is required + Experience...the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear… more
- Google (Mountain View, CA)
- …+ Experience with logic synthesis techniques to improve RTL code, performance and power as well as low- power design techniques. + Experience with ARM-based ... SoCs, interconnects and ASIC methodology. + Experience with a scripting language like...interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with… more
- Google (Madison, WI)
- …specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will be part of a team ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
- Google (Madison, WI)
- …focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will use your design and verification ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
- Google (Mountain View, CA)
- …like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical ... industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL… more
- Google (Sunnyvale, CA)
- …ASICs. + Experience in memory subsystem design verification. + Experience in Power aware verification, Gate level simulations, and Post silicon bring-up. + ... Familiarity with ASIC standard interfaces and memory system architecture. In this...team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to… more
- Google (San Diego, CA)
- …high complexity silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + Effective ... of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the… more
- Broadcom (Broomfield, CO)
- …high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency ._** **_We are looking for highly skilled and ... efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an… more
- NVIDIA (Santa Clara, CA)
- …power data, and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA... power analysis tools, to help improve product power efficiency . + Develop and share best… more
- NVIDIA (Santa Clara, CA)
- …power data and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies to ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- NVIDIA (Santa Clara, CA)
- …pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency . + Develop and share best practices for performing pre-silicon ... We are now looking for a Power Architecture and Optimization Engineer -...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- Power Device Corp (Bohemia, NY)
- Principal Electrical Engineer - Analog/Digital/ Power Electronics Department:NY Engineering Location:Bohemia, NY For more than 50 years, Power Device ... tool, component, or technology improvements for quality, timeliness, and efficiency . + Conduct in-depth technical interviews and make hiring...Charge Pump, Inverters using MOSFET, IGBT, SiC and GaN Power devices. + Analog / mixed signal ASIC… more
- NVIDIA (Santa Clara, CA)
- …a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency , and innovation. From our roots as a groundbreaking graphics company, ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team....Build roadmaps of system level features to address low power , low noise, perf/watt efficient product needs by doing… more
- Qualcomm (Austin, TX)
- …and interfaces + Great understanding of design techniques for speed and for power efficiency + Oversee definition, design, verification, and documentation for ... as the PC and the Data Center markets. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or… more