• Chip Integration Engineer

    Broadcom (San Jose, CA)
    …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The ... and routing ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks, soft/hard IPs, IOs, and… more
    Broadcom (11/19/25)
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  • Design Engineer - Chip Floorplanner

    Broadcom (Fort Collins, CO)
    …through production. **Role Overview** This Floorplanning Engineer role focuses on chip -level physical architecture and integration for advanced ASICs in deep ... to ensure clean tapeout readiness. + Coordinate with block owners and integration teams for smooth block-level to top-level convergence. + Support cross-functional… more
    Broadcom (12/16/25)
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  • Chip Architect

    Texas Instruments (Dallas, TX)
    …the chip architecture to meet all project requirements. + Own the chip top-level integration . Drive the integration process from architectural definition ... to ensure all project deliverables meet requirements and schedules, and to ensure smooth integration according to plan. **Why TI?** + Engineer your future. We… more
    Texas Instruments (11/07/25)
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  • MTS Packaging Integration Engineer

    Global Foundries (Malta, NY)
    …more information, visit www.gf.com. Summary of Role: This hands-on assembly integration role will deliver industry leading electro-optical transceivers using GF's ... on tool process interactions for each assembly step in a SiPh Flip Chip assembly. Focus on product and module reliability, package risk factors, packaging design… more
    Global Foundries (01/08/26)
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  • Senior Device Design & Integration

    Renesas (Goleta, CA)
    Senior Device Design & Integration Engineer Job Description This role will work in our Device and Product Group supporting New Technology Introduction (NTI) of ... our next-gen GaN semiconductor devices. The engineer will be responsible for high-voltage device design (including epi materials), chip layout, FET selection,… more
    Renesas (12/20/25)
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  • Staff Process Integration Engineer

    Micron Technology, Inc. (Boise, ID)
    …nodes, maintaining Micron's leadership in the industry. **Role overview:** As a Staff Process Integration Engineer in APTD at Micron, you will own the end‑to‑end ... development and transfer support. **Responsibilities:** + Own package‑level process integration across 2.5D/3D flows (wafer-to-wafer, chip -to-wafer, advanced… more
    Micron Technology, Inc. (01/10/26)
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  • Staff Device Design & Integration

    Renesas (Goleta, CA)
    Staff Device Design & Integration Engineer Job Description This Device Design and Integration Engineer will work on the design and the implementation of ... for the choice of GaN epitaxial structures, the device dimensions, the chip layout and package considerations to meet cost, performance and reliability… more
    Renesas (12/20/25)
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  • MTS Process Integration Engineer

    Micron Technology, Inc. (Boise, ID)
    …maintaining Micron's leadership in the industry. **Position Overview:** As a Process Integration Engineer for Advanced Packaging, you will own the end-to-end ... integration of next generation package architectures like 2.5D, 3D stacking, HBM memory integration , and hybrid bonding. You'll lead new technology development… more
    Micron Technology, Inc. (01/07/26)
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  • Light Source Integration Engineer

    Cisco (Carlsbad, CA)
    …provide a unique opportunity to seek modes of improvement that span from photonic chip design to optical assembly (ie, integration of fibers, light sources, ... part of a world class photonics team on the integration of Cisco's silicon photonics into our automated, high-volume...photonics manufacturing platform. Who You Are: You are an engineer or scientist with experience in one or more… more
    Cisco (11/27/25)
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  • Senior Test and Integration Engineer

    Leidos (Linthicum, MD)
    **Description** Leidos is currently looking to add a Test and Integration Engineer to a Cyber Security Program near Ft. Meade, MD. This challenging position ... complex, mission-critical Program. The successful candidate willperform the installation, integration , and test of operational equipment/software to verify compliance… more
    Leidos (11/07/25)
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  • Mixed-signal ASIC Design and Integration

    IBM (Yorktown Heights, NY)
    …advanced high-performance circuits in advanced node for exploratory applications * Chip integration experience leveraging mixed-signal analog-on-top (AoT) or ... applications. Experience with mixed-signal analog-on-top (AoT) or digital-on-top (DoT) integration design flows that leverage EDA-driven digital circuit design… more
    IBM (11/22/25)
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  • Post Silicon Hardware System Integration

    NVIDIA (Santa Clara, CA)
    …and help define the future of computing. We seek an experienced Post-Silicon Hardware Engineer to join our Silicon Solutions Group. In this role, you will validate ... meet aggressive schedules. + Cross-Functional Impact - Partner with architects, chip /board designers, firmware/software engineers, and QA to drive design, debug, and… more
    NVIDIA (11/05/25)
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  • Signal and Power Integrity Engineer , PhD,…

    Google (Sunnyvale, CA)
    …its integration within AI/ML-driven systems. As a Signal Integrity/Power Integrity Engineer , you will lead chip and package design, ensuring optimal Signal ... Signal and Power Integrity Engineer , PhD, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving… more
    Google (12/16/25)
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  • Package Design Engineer

    Google (Sunnyvale, CA)
    …shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration . As a Chip Package Designer on the Silicon ... Package Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid**...equivalent practical experience. + 4 years of experience in chip package substrate design using Cadence APD (Allegro Package… more
    Google (12/20/25)
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  • SoC Silicon Top-Level Floorplan Engineer

    Google (Sunnyvale, CA)
    …10 years of experience in physical design (eg, with a focus on floorplanning, integration , or top-level chip assembly). + Experience in physical design working ... SoC Silicon Top-Level Floorplan Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced**...timing/congestion closure for complex modern SoCs. You will utilize full- chip planning and IP integration , delivering floorplan… more
    Google (12/20/25)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    We are now looking for a CPU Design Methodology Engineer ! The complexity of chip development has greatly increased over the years. We are now packing tens of ... The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration , and chip build and assembly. You should be… more
    NVIDIA (01/10/26)
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  • Principal/ Senior Principal Digital ASIC Circuit…

    Northrop Grumman (Jessup, MD)
    …Degree - either MS or PhD + Current security clearance or eligibility + Experience with chip level integration and ASIC chip lead - Strong design automation ... the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom digital circuits....or PhD + Current security clearance + Experience with chip level integration and ASIC chip more
    Northrop Grumman (12/05/25)
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  • AI Software Research Engineer

    IBM (Yorktown Heights, NY)
    …company's AIU Spyre accelerator software stack. * Contribute to the PyTorch backend integration for the Spyre chip . * Contribute to hardware-software co-design, ... **Introduction** **Your role and responsibilities** AI Software Research Engineer , IBM Corporation, Yorktown Heights, NY: * Improve and optimize the… more
    IBM (01/07/26)
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  • Digital Design Engineer

    Meta (Austin, TX)
    …or block level uArchitecture definition and RTL implementation 2. Contribute to chip -level integration , verification plan development and verification 3. Define ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...static timing analysis 4. Support the test program development, chip validation and chip life until production… more
    Meta (01/10/26)
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  • Entry Level Signal and Power Integrity/System…

    IBM (Rochester, MN)
    …through high-speed serial channel analysis, power domain analysis, and 1st level chip packaging integration methodologies that enable hardware in IBM Mainframe ... for an entry level Signal and Power Integrity/Hardware Development Engineer . As a member of this elite team of...of this department partner with IBM Research on Custom Chip /Wafer Scale Integration and Quantum Cryogenic hardware… more
    IBM (01/07/26)
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