- Qualcomm (Austin, TX)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with implementation and ... CAD teams to implement the designs meeting aggressive power , area and performance goals using industry standard tools/flows for next generation CPUs.… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical ... and below process technologies. Nice to haves: + Knowledge of lower power digital design techniques. + IP integration experience. + Experience in data parallel… more
- NVIDIA (Santa Clara, CA)
- …experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, ... varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + Key responsibility… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's ... Timing. + Good knowledge of extraction, device physics, STA methodology and EDA tools limitations. Good understanding of mathematics/physics...electrical design . + Clear understanding of low power design techniques such as multi VT,… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... You will be responsible for all aspects of front-end design implementation methodologies (synthesis, formal-equivalence-checking), flow automation and application… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... memory BIST, scan and array dump and DFX security methodology . + In addition, you will help develop and...exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power , to ensure… more
- NVIDIA (Santa Clara, CA)
- …today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to ... design needs to balance high frequency clocks with power , DFT, noise, circuit and physical design constraints. What you'll be doing: + Develop Clock RTL… more
- NVIDIA (Santa Clara, CA)
- …+ Engage with EDA providers on 3D-IC EDA feature requirements and 3D-IC design methodology . + Design optimization of 3D advanced silicon/package ... 3D-IC Test Chips validation of 3D-IC technology platforms and design methodology . What we need to see:...and/or Product designs. + Multiple clock domain and Low Power Design . + Expertise with Python, TCL… more
- NVIDIA (Santa Clara, CA)
- …memories and IOs + Good exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power , to ensure we are making the right ... We are now looking for a Senior DFT Engineer ! NVIDIA has continuously reinvented itself over two...and intelligence. Make the choice to join us today. Design -for-Test Engineering at NVIDIA works on groundbreaking innovations involving… more
- NVIDIA (Santa Clara, CA)
- …using vendor tools. + Good exposure to multi-functional areas including RTL & clocks design , STA, place-n-route and power . + Experience in Silicon debug and ... intelligence. Make the choice to join us today. DFX Methodology Group at NVIDIA works on groundbreaking innovations involving...years of experience in DFT, system architecture, or RTL design . + Understanding of fundamental DFT topics, such as,… more
- ManpowerGroup (Phoenix, AZ)
- **Job Title:** **Physical Design - Power Integrity Flow Development Engineer ** **Location:** + **Primary:** Phoenix, AZ + **Secondary:** Remote in the US. ... (5nm and below). + Resolve power and power integrity issues related to physical design ,...issues related to physical design , identify potential low- power solutions, and drive execution and methodology … more
- Qualcomm (San Diego, CA)
- …- Strong background in system and hardware design . - Strong background in power methodology , power architecture, clock & reset arch, power ... smarter, connected future for all. As a Qualcomm GPU Engineer , you may architect, design , implement, verify,...Science, Engineering, or related field. - 7+ years of power design , power management &… more
- Google (Sunnyvale, CA)
- …delivering unparalleled performance, efficiency, and integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip ... testing, next generation memory, chiplet standards and timing budget methodology . Be part of a diverse team that pushes...package design with signal/ power integrity simulation and characterization… more
- NVIDIA (Santa Clara, CA)
- …GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design , methodology and AI based power optimization solutions. ... We are now looking for a Power Architecture and Optimization Engineer -...concepts of energy consumption, estimation, data movement and low power design . + Familiarity with Verilog and… more
- Qualcomm (San Diego, CA)
- …model development and formal verification (property checking). Learn and deploy power -aware UPF verification flow and methodology . Involve in developing ... or a closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + Master's… more
- Meta (Sunnyvale, CA)
- …complex solutions in future Meta products. **Required Skills:** Signal Integrity Power Integrity Engineer Responsibilities: 1. Lead pre-layout and post-layout ... Meta Smart Glasses team seeks a Signal Integrity / Power Integrity specialist with deep simulation skills and consumer...interface and PDN, create simulation models and develop simulation methodology for SIPI design 2. Lead SIPI… more
- Kimley-Horn (Orlando, FL)
- **Overview** Kimley-Horn'sOrlando, Florida (FL) office is seeking a Power Studies Engineer with 4+years experienceto join their Electrical team.With a focus on ... serving clients within thepower delivery andrenewable energy sectors, the Power Studies Engineer will act as a...Short Circuit, and Arc Flash studies basic theory and methodology + Proficiency using Computer-Aided Design and… more
- Ford Motor Company (Dearborn, MI)
- …autonomy, electrification, smart mobility technologies, and more! In this role, the Power Electronics Manufacturing Process Engineer will work with Product ... of power electronics assemblies. This role will have direct impact over the design and processing of power electronics assemblies in future Ford products. At… more
- Microsoft Corporation (Redmond, WA)
- …is looking for a **Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer ** to work as digital Application Specific Integrated ... We are looking for **Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer ** who is as passionate about their own contribution… more
- Qualcomm (Santa Clara, CA)
- …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design ... develop timing constraints, drive implementation of the designs to meet aggressive power , area and performance goals using industry standard tools/flows. One of your… more