- Eridu Corporation (San Francisco, CA)
- …of the first augmented reality contact lens). Position Overview We are seeking an RTL Packet Buffering to help define and implement our industry-leading ... specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities: Packet Buffering Design: Design and architect solutions… more
- Eridu Corporation (San Francisco, CA)
- A Silicon Valley hardware startup is looking for an experienced RTL Packet Buffering engineer to design and implement cutting-edge Networking IC ... solutions. This role includes responsibilities such as designing high-speed networking chips with a focus on latency optimization and protocol support. The ideal candidate has 8-15 years of experience and works proficiently with SystemVerilog and Verilog,… more
- FLIR Systems, Inc. (Milpitas, CA)
- …** RTL Design & Microarchitecture** + Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, ... Staff Logic Design Engineer page is loaded## Staff Logic Design Engineerlocations:...design for FPGA or ASIC.* Strong proficiency in **Verilog/SystemVerilog RTL design**.* Experience with one or more of the… more
- Teledyne (Milpitas, CA)
- …+ ** RTL Design & Microarchitecture** + Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and ... We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience,...for FPGA or ASIC. + Strong proficiency in **Verilog/SystemVerilog RTL design** . + Experience with one or more… more
