- SpaceX (Bastrop, TX)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Bastrop, TX)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... Sr. SOC / ASIC Timing Signoff & Front-End Implementation...+ Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +… more
- SpaceX (Irvine, CA)
- SOC / ASIC Timing Signoff & Front-End Implementation...and understanding of their impact on physical design and timing closure + Familiar with ASIC ... the ultimate goal of enabling human life on Mars. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER...change order flows (Timing ECOs) and integrate them into physical design flow + Work with systems… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Physical Design Engineers...design of an end-to-end IP or integration of ASIC / SoC design and point out ... ) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities:...Knowledge of geometry/process/device technology implications on physical design . 16. Experience with large SOC designs… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- Amazon (Redmond, WA)
- …ASIC / SOC leads) to create project execution plans for ASIC / SOC development considering all criteria to design products the meet the power/performance ... for a Sr. Technical Program Manager with experience in ASIC / SOC development, from architecture to pre-production stages,...from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring… more
- SanDisk (Milpitas, CA)
- … development + Contribute to the development of best practices and methodologies for ASIC design within the organization + Optimize designs for power efficiency, ... architectures using advanced RTL techniques + Develop and optimize SoC subsystems, including CPU complex, DDR, Host, Flash, Debug,...design optimization + Proficiency in EDA tools for ASIC design and verification + Knowledge of… more
- Meta (Austin, TX)
- …( ASIC Development tools, Compute/Storage/Licensing management,etc.) and/or CAD Methodology ( Physical Design , Timing Methodology, Physical Verification, ... and Enterprise Engineering teams on adapting FB infrastructure to ASIC design solutions, including but not limited...Experience managing environments for concurrent development of IP and SOC releases and working with cross functional teams to… more
- Qualcomm (San Diego, CA)
- …low power designs. + Strong knowledge in the entire low power, high performance ASIC / SoC design flows (micro-architecture, RTL design , verification, ... PrimeTime PX (PTPX) and work with cross-functional teams - design , implementation, and physical design ...Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related… more
- Meta (Sunnyvale, CA)
- …Responsibilities: 1. Front End implementation flow development and support. 2. Physical Design implementation flow development and support. 3. RTL2GDS ... ASIC infrastructure to build efficient System on Chip ( SoC ) and IP for data center applications. **Required Skills:**...tools development and automation to help improve productivity across ASIC design cycles including but not limited… more
- Amazon (Austin, TX)
- …- Drive technical decisions across multiple disciplines (RTL, timing, DFT, physical design ) - Ensure on-time delivery of complex SOC integration milestones - ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze...Strong background in power/performance optimization and physical design considerations - Experience with modern SOC … more
- Meta (Austin, TX)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... teams and vendors. **Preferred Qualifications:** Preferred Qualifications: 16. Experience with SOC Design Integration and Front-End Implementation. 17. Knowledge… more
- Meta (Austin, TX)
- …Emulation Engineers in supporting them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing feedback. **Minimum ... teams and vendors. **Preferred Qualifications:** Preferred Qualifications: 16. Experience with SOC Design Integration & Front End Implementation 17. Experience… more
- Meta (Sunnyvale, CA)
- …Engineers in supporting them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing/congestion feedback. **Minimum ... to joining Meta **Preferred Qualifications:** Preferred Qualifications: 19. Experience in SOC Design Integration and Front-End Implementation. 20. Knowledge of… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... practical experience **Preferred Qualifications:** Preferred Qualifications: 17. Experience in SOC Design Integration and Front-End Implementation. 18. Knowledge… more
- Qualcomm (San Diego, CA)
- …system-level in 5nm, 4nm and beyond (process technologies). + You will be working with physical design team (and other teams) on timing closure, CAD teams, IP ... Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR… more
- Qualcomm (San Diego, CA)
- …The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate ... **Responsibilities/Duties:** + Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of...Science, Engineering, or related field and 2+ years of ASIC design , verification, validation, integration, or related… more
- SanDisk (Irvine, CA)
- …and reviewing **low-level firmware** in C/C++ and/or Python + Solid understanding of ** SoC design ** and processor architectures (eg, ARM, ARC) + Familiarity with ... for a **PCIe expert** with a strong background in ** ASIC and Firmware development** to help define, architect, and...products. In this high-impact role, you will drive the design of advanced SSD subsystems, write detailed specifications, and… more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more