- NVIDIA (Austin, TX)
- …and intelligence. The NVIDIA System-On- Chip (SOC) group is looking for a top Senior ASIC Verification Engineer! In this position you will have the chance to ... and SOC). What you'll be doing: + Design and maintain the Full Chip Verification environment. + Understand the architecture specifications and develop the test… more
- Cisco (San Jose, CA)
- …and verification processes, debugging, methodology, and tools. * Experience in verifying blocks/clusters/ full chip level for ASIC . Preferred: * Post-silicon ... Who You'll Work With You will work with outstanding talent and vast ASIC development expertise in design, DV, DFT, physical design, and post-silicon validation The… more
- SpaceX (Irvine, CA)
- …will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: + Full chip and block level timing signoff and convergence through timing ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon...post routed database for various timing signoff checks + Full chip and block level front-end implementation… more
- Cisco (San Jose, CA)
- …Verilog RTL to meet timing, performance, and power requirements. * Contribute to full chip integration and timing methodology/analysis. * Develop and analyze ... Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a...breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact * Write micro-architecture… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to… more
- NVIDIA (Santa Clara, CA)
- …and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Work with PD, DFX, Clocks, and other teams in coming ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Timing and STA + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA)… more
- Cisco (San Jose, CA)
- …* End-to-end verification of one or more design blocks simultaneously while helping the full chip team with integration and support. * Test plan generation, ... in the world. You will engage in dynamic collaboration with Senior micro-architects, designers, and verification engineers and interact with cross-functional… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic ... of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.… more
- Amazon (Austin, TX)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more
- Amazon (San Diego, CA)
- …applying sound business judgement combined with technical acumen. * Analyze Silicon Chip industry package and ATE trends and emerging technologies to identify ... solve IP ownership, capability and operational barriers. * Drive ASIC package, ATE, Qualification/FA Engineering/Consulting Services supplier strategies and… more
- Tarana Wireless (Milpitas, CA)
- …software engineers to define verification strategies and execute plans at system or full chip level + Build and continuously improve verification infrastructure ... and methodologies to meet the demands of next generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project Ways to stand out from the crowd: + Ability… more
- Amazon (Austin, TX)
- …change the world. Annapurna Labs is looking for a Sr. Packaging Engineer. As a senior member of the team, you will join a group of hardworking engineers to design ... teams, software engineers to deliver the next generation ML chip . In this position, you will have the opportunity...collaboration with Package Design team and OSATs - Assume full ownership of mechanical and thermal performance of Annapurna… more
- Capgemini (CA)
- …our business with semiconductor clients through comprehensive solutions in chip design, software, hardware, supply chain, and sustainability. **Key ... technology needs aligned with customer product roadmaps. + We engage with senior management levels to strategize pursuits, develop account maps, and identify target… more
- Qualcomm (Santa Clara, CA)
- …The candidate will work hands-on and own their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, ... correlation. The candidate will also be responsible for the full chip debug design using ARM IPs....will work hands-on and own their design through the full ASIC development process from specification, RTL… more
- Palo Alto Networks (Santa Clara, CA)
- …and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi- chip -module designs + Model and analyze power delivery networks ... in-person interactions. This is why our employees generally work full time from our office with flexibility offered where...the Hardware team, you collaborate closely with Board Design, ASIC Design, PCB Layout, and Validation Test. You will… more
- Fortive Corporation (Beaverton, OR)
- …+ **Design:** Develop and manage large analog and mixed signal blocks and full chip schematics. + **Layout Design:** Design sensitive layouts and assist ... Analysis:** Perform signal analysis on systems external to the ASIC . + **Characterization:** Characterize designs or generate comprehensive characterization plans.… more
- Google (San Diego, CA)
- …ARM, x86, RISC-V, etc.) and Internet Protocols (IPs) used in System on a Chip (SoC) designs. + Experience with C/C++. Preferred qualifications: + Master's degree or ... and development for software layers found in Application-specific integrated circuit ( ASIC ) (eg, boot, drivers, embedded firmware, libraries, and API for… more
- Micron Technology, Inc. (Richardson, TX)
- …the DDR or LPDDR design is based on the gate-level design only while the Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) ... HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via).… more
- Google (Sunnyvale, CA)
- …Gemini models to enterprise customers. The US base salary range for this full -time position is $147,000-$216,000 + bonus + equity + benefits. Our salary ranges ... on data center hardware products. + Collaborate with board, chip and system engineers, design partners and chip...and ensure that product functions as required. + Drive ASIC , package, board, connector, and cable vendors to develop… more
- quadric.io, Inc (Burlingame, CA)
- …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of ... Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + BS/MS or Ph.D.… more