- Intel (San Jose, CA)
- …ensure our silicon products meet the highest quality standards for high-volume manufacturing. As a Senior DFT Design Engineer , you will be responsible ... Overview We are seeking a senior skilled DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our… more
- Intel (San Jose, CA)
- A leading semiconductor company in California is seeking a Senior DFT Design Engineer to develop and optimize comprehensive Design for Test ... ensure product quality and innovative testing solutions, while leveraging expertise in DFT methodologies such as SCAN, MBIST, and BSCAN implementations. The ideal… more
- Microchip (San Jose, CA)
- Senior Technical Staff Engineer - Design for Test Company Description Are you looking for a unique opportunity to be a part of something great? Want to join ... during test and quantifying full chip test coverage. Establish and maintain DFT design and insertion guidelines and documents best practices for all development… more
- Altera (San Jose, CA)
- …us in our journey to becoming the world's #1 FPGA company!Altera is seeking a ** Senior Design Automation Engineer ** to join our Design Methodology ... maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior... design methodologies spanning Front-End, handoff to Backend, Design Verification, Design -For-Test ( DFT ), … more
- Pratt & Whitney (Boston, MA)
- …our mission today. This position is for a motivated Electrical or Computer Engineer to be involved in the design , implementation, verification, and integration ... ASIC / FPGA lab validation with advanced lab equipment Design for Test ( DFT ) and manufacturability issues Experience with Unix, scripting, C/C++, and/or… more
- Vivid Technology (San Jose, CA)
- …quality standards (FuSa, AEC‑Q100, ISO 26262) Support synthesis, STA, clock‑domain crossing, low‑power design , and DFT with physical design teams Ensure ... technology. Key Qualifications 10+ years hands‑on experience in digital design with the understanding of analog and mixed‑signal IC... with the understanding of analog and mixed‑signal IC design , ideally in CMOS technologies at 28nm TSMC Expertise… more
- Bitdeer Group (Washington, DC)
- …reports. Support mass‑production readiness by working with manufacturing and suppliers for DFM ( Design for Manufacturing) and DFT ( Design for Testability) ... involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company… more
- Qualcomm (San Diego, CA)
- AI for Yield & Diagnostics, Senior Staff Engineer Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, ASICS Engineering General Summary: As a ... We are seeking a highly motivated and technically skilled AI Applications Engineer to help lead the development and deployment of artificial intelligence solutions… more
- Qualcomm (San Diego, CA)
- …structure large-scale test and yield datasets. Integrate data from ATE (Automated Test Equipment), DFT ( Design for Test), and fab & assembly process logs for ... We are seeking a highly motivated and technically skilled AI Applications Engineer to help lead the development and deployment of artificial intelligence solutions… more
- Efficient Computer (San Francisco, CA)
- …evolution of computing, we would like to talk to you. Efficient is hiring a senior ASIC Physical Design Engineer with experience in backend implementation ... If you are an ASIC Physical Design Engineer who wants to impact...and functional Engineering Change Orders (ECOs). Engage with the DFT team to plan and provide early feedback on… more
- Aleron (San Diego, CA)
- Overview We are looking for a highly motivated, creative and experienced ATE Test Engineer to design and implement automated test solution for RF connectivity ... best in class test cost (COT) towards overall product cost. Collaborate with design and DFT teams to define test plans and optimize test coverage for RF and… more
- Cadence Design Systems, Inc. (Austin, TX)
- …are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain insertion, ... of professional experience in SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT insertion flows +… more
- Microsoft Corporation (Hillsboro, OR)
- …manage and optimize the Cloud infrastructure. We are looking for a ** Senior Design for Test ( DFT ) Engineer ** to join the team. **Responsibilities** + ... experience. + 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test + ATPG, JTAG, Memory BIST, and trade-offs… more
- Microsoft Corporation (Raleigh, NC)
- …solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior DFT Engineer to join the team. **Responsibilities** + Execution ... across multiple projects, ensuring alignment with overall chip design goals. + Define and implement DFT ...chip design goals. + Define and implement DFT architecture, including scan insertion, boundary scan, MBIST, and… more
- Renesas (Austin, TX)
- Senior Staff DFT Engineer Job...to ATE + Coordinate with other Engineering disciplines + Design to ensure DFT approach is effective and ... datacenter. **What we need:** We are seeking a Mixed-Signal DFT Engineer to ensure efficient, high-coverage, testability...+ Ensure integrity in observability and controllability of each design block to/from the pins of the part +… more
- Celestica (Richardson, TX)
- …State/Province: Texas City: Richardson **Summary** We're searching for a dynamic and experienced Functional Design for Test ( DFT ) Engineer to join our team ... performance. + Drive insights through Functional DFT ( DFT -F) analysis, providing critical recommendations for design ...positive team with a balanced mix of young and senior experts + Various Celestica benefits: You will have… more
- SpaceX (Sunnyvale, CA)
- …extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr. SOC/ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA...leveraging Siemens Tessent tools + Integration and verification of Design for Test ( DFT ) IPs and fabrics… more
- NVIDIA (Santa Clara, CA)
- …with 5+ years, MSEE with 3+ years, or PhD with 2+ years of experience in DFT , system architecture, or RTL design . + Understanding of fundamental DFT topics, ... Excellent understanding of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe… more
- NVIDIA (Santa Clara, CA)
- …imagination and intelligence. Make the choice to join us today. Design -for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative ... solutions for DFT architecture, verification and post-silicon validation on some of...exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power, to ensure we are… more
- Northrop Grumman (Linthicum Heights, MD)
- …to obtain and maintain an active clearance.** **Roles and Responsibilities:** + Responsible for DFT ( Design for Testabilty) aspects of ASIC Design thorough ... and Static Timing Analysis would be a plus + Active Clearance or higher ** Senior Principal Engineer Basic Qualifications:** + Bachelor's degree with 8 years of… more
