- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy constraints checks. We're looking… more
- NVIDIA (Santa Clara, CA)
- …field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology , or constraint development. + Strong expertise in asynchronous ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Qualcomm (San Diego, CA)
- …Engineering, or related field. **Job Description:** + Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu ... emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance. + Drive debug failures...debug. + Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA… more
- Northrop Grumman (Linthicum Heights, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug ** Senior Principal Engineer Basic Qualifications:** + Bachelor's ... for you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification Engineer based out of Linthicum, MD or Morrisville,… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
- Palo Alto Networks (Santa Clara, CA)
- …the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or ... digital logic blocks and subsystems. + **Design** high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets, with… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Qualcomm (Austin, TX)
- …on use cases + RTL and Synthesis based Power Optimization + Thermal Analysis and Optimization + Performance Power and Area modeling and optimization + SOC Design ... responsible for all aspects of power estimation/implementation/verification/minimization and associated methodology /flow development. The focus will be on delivering best… more
- Qualcomm (Santa Clara, CA)
- …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and ... IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and… more