- Silvus Technologies (Irvine, CA)
- …a pathway to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA/ RTL Design Engineer_** who will report to the _Director of FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Silvus Technologies (Irvine, CA)
- …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer- Signal Processing_** who will report to the _Senior ... fields. + Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years...systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. + Occasional exposure to… more
- Microsoft Corporation (Redmond, WA)
- …experience to customers and partners worldwide and we are looking for a ** Senior RTL to** ** Physical Design Engineer** to help achieve that mission. The ... to Microsoft cloud hardware. We are looking for a ** Senior RTL to Physical Design Engineer** with a passion for customer focused solutions, insight… more
- Broadcom (Fort Collins, CO)
- …power and most advanced wireless solutions, as some examples. The _Interface and Analog IP RTL Design Manager_ position is part of a cross functional design ... the IP. This manager will work closely with the physical design team that builds the ...+ Lead & manage a team of high performance RTL design engineers in the development of… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and ... projects aimed at addressing challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at Silvus' Irvine CA… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog ... the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered. Position...limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification… more
- Northrop Grumman (Jessup, MD)
- …, implementation, test) of ASIC design + Working knowledge of the front-end ASIC design flow from RTL to gates ( RTL coding, simulation, synthesis, static ... constraints and timing closure. Automated place and route and physical verification knowledge is a plus. Must have strong...Excelium, Incisive or Synopsys VCS - Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL … more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer who is dedicated ... and implement design fixes to ensure physically-viable RTL netlists are delivered to downstream physical design flows. + Project level cell library… more
- Microsoft Corporation (Mountain View, CA)
- …converged solutions, automation, and quality assurance checks across front-end areas like RTL & VIP Design , Design Verification, Validation, DFT, ... Emulation, Design Synthesis, RTL Power Anaysis, PD Handoff and SoC integration. This...can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer, you'll drive the development and… more
- Cisco (Maynard, MA)
- …Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues related to design , tools, etc. * Evaluate and implement ... smaller ASIC team can provide. Your Impact As a Physical Design Engineer, you will play a...you will play a key role in the full RTL -to-GDSII implementation flow for advanced semiconductor nodes. You will… more
- NVIDIA (Austin, TX)
- …in Perl/Python or other industry-standard scripting languages + Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design ... applying the performance monitoring system + Run and debug RTL checks to ensure design quality (eg,...on silicon debug is a plus. + Exposure to physical design With competitive salaries and a… more
- NVIDIA (Santa Clara, CA)
- … design . + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers to accomplish your goals. ... We are looking for a Senior ASIC Design Engineer to join...bandwidth data paths. + A deep understanding of ASIC design flows including RTL design ,… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic ... intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,...Deep understanding of hardware architecture and hands-on skills in RTL /logic design for timing closure. + Experience… more
- NVIDIA (Santa Clara, CA)
- …clocking, and power management solutions. + You'll drive the design and physical implementation of custom digital IPs from RTL to layout using industry ... We are now looking for a Senior Circuit Design Engineer! NVIDIA stands...entire silicon design flow, from micro-architecture and RTL design to back-end execution, including Custom/Semi-Custom… more
- Capgemini (San Jose, CA)
- …- Bay Area CA** **About the Job You're Considering** 1. Hands-on experience with ** RTL design ** and **Vivado Flow (IP Integrator)** . 2. Strong **debugging ... and validation. **Your Skills and Experience** 1. Proficiency in ** RTL design ** and **Vivado Flow (IP Integrator)**...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
- NVIDIA (Santa Clara, CA)
- … design , Verilog and/or System-Verilog with a deep understanding of physical design and VLSI + Experience with RTL development, Custom Digital Design , ... We are now looking for a motivated Senior ASIC Design Engineer to join...performance of NVIDIA's next generation GPUs + Partner with RTL and Design Verification engineers to ensure… more
- NVIDIA (Santa Clara, CA)
- …Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL . + Collaborate with Physical design and timing team to ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...ability to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis.… more
- Palo Alto Networks (Santa Clara, CA)
- …coverage, and add design -for-debug features. + **Partner** with physical - design teams: review synthesis/timing reports, rewrite RTL to close critical ... from specification through silicon bring-up, working with world-class verification and physical - design engineers to hit aggressive performance, power, and… more
- NVIDIA (Hillsboro, OR)
- …will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. What you will be ... We are looking for a Senior CPU Design Engineer! NVIDIA is...synthesis/timing clean design while working with the physical design team ensuring a routable and… more
- NVIDIA (Santa Clara, CA)
- …in the front-end chip implementation process and propose actionable improvements + Ensure high-quality RTL delivery to the physical design team with thorough ... integrating advanced ASICs, and partnering with experts in ASIC design , Physical design , CAD, Package...+ Strong analytical and problem-solving skills + Expertise in RTL design , SOC integration, and design… more
