- The Boeing Company (El Segundo, CA)
- …with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a ** Static Timing Analysis (STA) Engineer** to join us as part of ... support more Boeing Platforms. We are seeking an experienced Static Timing Analysis Engineer that...around the world from the early design stages until signoff to help achieve first pass success. You will… more
- SpaceX (Irvine, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- SpaceX (Bastrop, TX)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- Cadence Design Systems, Inc. (Austin, TX)
- …make an impact on the world of technology. In this senior role you will; Perform Static timing analysis , glitch, noise analysis using Tempus Signoff ... and customer sites. Requirements; 8+ years of experience in Static timing analysis , Individual should...Tempus - Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Cisco (Maynard, MA)
- …CTS, routing) + Power, performance and area optimization of design + Static Timing analysis and signoff closure + Physical verification and signoff ... design cycle from RTL to GDSII + Understanding of Static Timing Analysis , timing...+ Knowledge in block level synthesis, place and route, timing closure, PnR and signoff tools and… more
- Microsoft Corporation (Hillsboro, OR)
- …hands-on experience. + Good understanding of timing constraints (functional & DFT), static timing analysis (STA), and timing -power optimization. + ... + Demonstrate technical expertise across various domains of Physical Design & Timing Signoff . + Clear communications on project status & planning. + Demonstrate… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get involved in design ... SDC Verification + Place and Route + Parasitic Extraction, Timing Signoff , Power Signoff +...Synopsys place and route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis ) + Debug… more
- Teradyne (North Reading, MA)
- …in the areas of electromagnetic field and transmission line theory, reflection and static timing characterization, PCB and IC Package design for power integrity, ... architectural feasibility, planning for signal and power integrity package signoff validation, performing detailed package and system interconnect optimization and… more
- Cisco (San Jose, CA)
- …experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure, ... post silicon validation phases with additional exposure to physical design signoff activities. **Key Contributions:** + Manages the definition, architecture and… more
- Google (Sunnyvale, CA)
- …+ Experience working with external partners on Physical Design (PD) closure. + Experience in Static Timing Analysis (STA), with an understanding of how to ... to GDSII, including key stages like floorplanning, place and route, and timing closure). + Experience in Python, Tcl, or Perl scripting. **Preferred… more
- SpaceX (Sunnyvale, CA)
- … budgeting and constraint pushdown to partition owners + Work with static timing analysis , physical verification, electromigration/voltage drop, noise ... and solutions (leakage power, signal integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeout +… more