- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- SpaceX (Bastrop, TX)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Qualcomm (Austin, TX)
- …of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and ... Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design -for-manufacturing & … more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. ... of ML accelerator at edge. Work hard. Have fun. Make history. As a Physical Design Engineer , you will: - Work with RTL/logic designers to drive architectural… more
- Google (Mountain View, CA)
- …or a related field, or equivalent practical experience. + 4 years of experience in Physical Design . + Experience in one or more synthesis/PnR tools (eg, Genus, ... + Experience with ASIC design flows and methodology of Physical design . + Experience in low power design Implementation including UPF/CPF,… more
- Qualcomm (San Diego, CA)
- …The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...**Responsibilities/Duties:** + Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of… more
- Capgemini (Seattle, WA)
- **Job Description:** We are seeking a SoC Design Verification Engineer to join our team 100% onsite in either Seattle, WA or Santa Clara, CA. The ideal ... digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of...**Organization:** _ERD PPL US_ **Title:** _Lead E/E & Semiconductor Engineer - SOC Design Verification… more
- Micron Technology, Inc. (Richardson, TX)
- …the lowest power per bit solutions in the industry. **Position Overview:** As a **Principal HBM SOC Design and Integration Engineer ** , you will design ... partners to ensure the success of our HBM roadmap. Your deep understanding of SOC Architecture, RTL Logic Design , IP Integration, high-speed interface design… more
- Google (Sunnyvale, CA)
- …generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team working ... on SoC -level RTL design for our data center accelerators. You will ...to verify and debug RTL designs. + Work with physical design teams to ensure design… more
- Qualcomm (San Diego, CA)
- …supervision. **Preferred Qualifications:** + Strong familiarity with Static Timing Analysis and Physical Design tools & methodology. + Solid understanding of ... Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a SoC Power/Performance Post-Si Validation & Emulation Engineer , you will be… more
- Qualcomm (San Diego, CA)
- …Cadence Innovus, Synopsis PTSI, etc.) to execute advanced architecture and implementation of design in the physical design environment of multiple complex ... blocks and makes suggestions for design improvements with respect to timing,... improvements with respect to timing, power analysis and physical verification. Develops an implementation strategy that meets system… more
- Capgemini (CO)
- …and management of constraints and exceptions. + Collaborate closely with block and SoC design teams to understand design requirements, STA constraints, ... **About the Job You're Considering** + Develop block-level and SoC -level timing constraints, and drive full-chip STA setup and... flows and analysis tasks. + Hands-on experience with physical design implementation is a plus. +… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... for next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a...collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs… more
- Meta (Sunnyvale, CA)
- …on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power… more
- Meta (Austin, TX)
- …on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of ... of several modules. + Integrate modules into the overall SOC design and work closely with other...CHI + Familiar with OCP secure boot specification and physical security handling process + Possess design … more
- SpaceX (Redmond, WA)
- FPGA/ASIC Design Engineer (Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...Starlink projects, implementing complex SoC blocks and SoC integration tasks + Implement or integrate design… more
- Qualcomm (Santa Clara, CA)
- … engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using ... technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU,… more
- Qualcomm (San Diego, CA)
- … design team to close IP block specification/requirement. + Work closely with verification/ physical design team to complete the IP design implementation. ... integrate low power / power management IP solution into wireless SoC chips and front-end design flows. + Work closely with system/software/test team to enable… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks +… more