- General Motors (Warren, MI)
- …+ Master's degree in Electrical Engineering / Electronics + Previous experience with SoC design /application on a module or component level + Knowledge of ... **Job Description** We are seeking a **_Senior Design Release Engineer (DRE)_** to lead...production readiness activities for our cutting-edge next generation _System-on-a-Chip ( SoC ) semiconductors_ . Your efforts will be on the… more
- Qualcomm (San Diego, CA)
- …to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, ... primary role is to implement and validate low power design intent requirements at the SoC -level. The...Computer Engineering plus: + ASIC frontend development + Logic design , RTL coding, verification, synthesis, and timing … more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a ... (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Work for...& Route and other local/remote teams to address the design challenges in the context of timing … more
- SpaceX (Irvine, CA)
- Sr. SoC Design Engineer , DSP... blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all ... ultimate goal of enabling human life on Mars. SR. SOC DESIGN ENGINEER , DSP IMPLEMENTATION...phases of ASIC and/or FPGA design flow (eg synthesis, timing closure, formality… more
- SpaceX (Redmond, WA)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON...design team to drive architectural feasibility studies, develop timing , power and area design targets, and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …annually using our products. The CSG Central Applications Engineering team seeks an experienced SoC design engineer to integrate and support Cadence IP ... IP integration. + Develop examples and best practices for SoC system design , verification, and testbenches for...System Verilog). + Experience in RTL synthesis and static timing analysis is required. + Strong written and oral… more
- SpaceX (Sunnyvale, CA)
- SOC /ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SOC /ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...synthesis, formal verification, power intent verification and post synthesis timing validation flows + Execute low power design… more
- Google (Sunnyvale, CA)
- …that goes into our cutting-edge data centers affecting millions of Google users. As a SoC Physical Design Engineer , you will collaborate with Functional ... that power all of Google's services. As a Hardware Engineer , you design and build the systems...with logic designers to drive architectural feasibility studies, develop timing , power and area design targets, and… more
- General Motors (Warren, MI)
- …experience in hardware design and development + Deep understanding of automotive SoC architecture, memory hierarchy, and ASIC design flow. + Knowledge of ... strong partnerships with internal and external stakeholders, guiding electronics design , and ensuring optimal semiconductor selections for GM applications. This… more
- Qualcomm (San Diego, CA)
- …+ Generate, review and validate clock domain crossing, design constraints to achieve timing closure of complex soc cores. + Tabulate metrics results for QOR ... processing transformation to help create a smarter, connected future for all. Qualcomm's SoC implementation team is seeking talented engineers to work on synthesis, … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... plans for NVIDIA's next generation of CPU, GPU or SOC designs. + Owning STA of large subsystems and...(or equivalent experience) with 2+ years experience in ASIC Design and Timing + Great understanding of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... checks, etc. + Help in all aspects of physical design , such as driving timing convergence, ...from the crowd: + Deep understanding of CPU, GPU, SOC architecture and designs as well as ability to… more
- Amazon (Sunnyvale, CA)
- Description As a ASIC Design Engineer , you work with a...in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional SOC ... design experience including owning end to end design of major SOC blocks - Successful...methodologies and EDA tools - Experience working with Synthesis, timing and design constraints Preferred Qualifications -… more
- Microsoft Corporation (Raleigh, NC)
- …servers, clients, and augmented reality. We are looking for a **Senior Physical Design Engineer ** to work on leading edge Intellectual Property (IP) development ... RTL-to-PD, you will be a key link between front-end design and System on Chip ( SOC ) back-end...design . + 4+ years of experience in synthesis, timing constraints and timing closure, front-end … more
- Qualcomm (San Diego, CA)
- …positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...will design , verify, and deliver complex Physical Design solutions from netlist and timing constraints… more
- NVIDIA (Santa Clara, CA)
- …(Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design , synthesis, timing + Silicon bring-up + SOC level integration What we need to ... design and implement the world's leading GPU and SoC 's. This position offers the opportunity to have a...understanding of ASIC design flow including RTL design , verification, logic synthesis and timing analysis… more
- Amazon (Redmond, WA)
- …or related field, or equivalent experience . 7+ years of experience in digital design , preferably in SoC design and implementation Preferred Qualifications ... comprehensive gate-level simulation test plans for verifying ASIC functionality and timing . Analyze simulation results, identify and debug logic errors, and propose… more
- NVIDIA (Santa Clara, CA)
- …high frequency clocks. + You should be able to engage with multiple teams and design the SOC clocks to satisfy all the architectural constraints. + Your ... with other team members, we deliver clock information to SOC verification team, timing and DFT teams....the above teams. + Collaborate with Software and product design team to debug SOC clock silicon… more
- NVIDIA (Santa Clara, CA)
- … Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoC 's and GPU's. This position offers you a ... unique opportunity to craft and to influence the design and development of the next generation GPU and SoC , allowing you to have real impact in a dynamic,… more
- SpaceX (Sunnyvale, CA)
- Sr. ASIC Design Engineer , DDR IP (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER , DDR IP (SILICON ENGINEERING) At...IP core development and integration + Responsible for RTL design , synthesis, timing constraints, power estimation, and… more