- Google (San Diego, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Experience in extraction of design ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Qualcomm (San Diego, CA)
- …Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define and ... for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge internal and EDA technologies in… more
- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 10 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Google (Sunnyvale, CA)
- … (eg, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk). Preferred qualifications: + 7 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Meta (Austin, TX)
- …experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and… more
- NVIDIA (Santa Clara, CA)
- …years experience in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …+ 8+ years experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and...+ You will be responsible for all aspects of timing including, timing analysis and… more
- NVIDIA (Westford, MA)
- … tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon...be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Qualcomm (Santa Clara, CA)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- Qualcomm (San Diego, CA)
- …also have experience with industry standard chip design tools and design flows for Static Timing Analysis , Spice / Fast spice simulation, Synthesis, DFT, ... automation skills. Hands-on experience in EDA tool automation, data analysis and visualization & large-scale software automation enablement. Excellent understanding… more
- NVIDIA (Austin, TX)
- …Engineering or Device Physics (or equivalent experience) + 8+ years experience in gate-level static timing analysis and/or power analysis + Proficiency ... algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale...algorithms for large scale and high accuracy gate-level power, timing , parasitic, and noise analysis . A deep… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools ... from concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- Qualcomm (San Diego, CA)
- …in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime toolset and should have ... power analysis and optimization, and IR drop analysis and optimization is also helpful. The engineer...signoff **Required Skills and Experience :** ⦁ Expertise in static timing analysis . Hands-on… more
- Northrop Grumman (Dulles, VA)
- …FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis , and power analysis + US Citizen ... they're making history. We have openings for a **FPGA/ASIC Engineer ** to join our team of qualified, diverse individuals...such as RTL/gate level simulation, synthesis, place and route, static timing analysis , and power… more
- Broadcom (San Jose, CA)
- …for intricate SoC designs. + Experience with Synopsys TCM tool. + Perform static timing analysis (STA) using industry-standard tools (eg, PrimeTime, ... Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be... timing checks and quality of results (QoR) analysis . + Automate timing analysis … more
- Meta (Austin, TX)
- …designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis , IR drop, EM, and physical ... and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical...H-Tree, and clock power reduction techniques 21. Knowledge of static timing analysis and concepts,… more