- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
- NVIDIA (Austin, TX)
- …design verification experience + Experience in pre-silicon verification ( UVM , SystemVerilog ), ASIC design /implementation flow, and design ... components using SV/ UVM methodology + Driving coverage-based verification closure + Collaborate with design teams...the crowd: + Previous experience automating tasks in the design verification process + Hands on experience… more
- Data Device Corporation (Bohemia, NY)
- …inVHDL;working knowledge ofVerilog, SystemVerilog and UVM for function verification . + FPGA Design Tools: Proficiency in Xilinx Vivado required; ... involves developing robust testbenches, creating advanced simulation environments, executing verification suites, and collaborating closely with Design Engineers… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Menlo Park, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Micron Technology, Inc. (Minneapolis, MN)
- …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
- Google (Sunnyvale, CA)
- …to identify important verification scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and UVM , or formally ... ASIC Design Verification Engineer, University Graduate _corporate_fare_...SystemVerilog for ASICs. + Experience in power aware verification , gate level simulations, and post silicon bring-up. +… more
- Northrop Grumman (Jessup, MD)
- …The Systems Engineering Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies ... verification processes. **Role And Responsibilities:** The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification … more
- BAE Systems (Nashua, NH)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- SpaceX (Sunnyvale, CA)
- Design Verification Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- Northrop Grumman (Linthicum Heights, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting...with Polygraph. + Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience Northrop… more
- Snap Inc. (Vancouver, WA)
- …AR + Work closely with digital design , analog logic, software and verification engineers + Develop and implement UVM -based and assertion-based testbenches + ... learning, and working better together. We're looking for a Design Verification Engineer to join the Spectacles...automation Knowledge, Skills & Abilities: + Strong knowledge of UVM and SystemVerilog for advanced verification… more
- Northrop Grumman (Linthicum Heights, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Familiarity with a...or PhD + Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience +… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Lockheed Martin (Denver, CO)
- …* Devise a unique verification plan for a given design \. * Use SystemVerilog and Universal Verification Methodology \( UVM \) to verify a design in ... Verification Engineer** who has a passion for microchip design and space\. - - - **Key activities you...need:** * ASIC/FPGA verification experience with modern verification methodologies such as UVM , OVM or… more
- Global Foundries (Richardson, TX)
- …years of experience in SoC verification . + Expertise in writing tests using SystemVerilog , UVM and C . + Experience with scripting languages like Python, ... more information, visit www.gf.com. Summary of Role: Seeking a Senior System-on-Chip Design Verification engineer to verify the High-Performance Data Processing… more