- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …JTAG preferred + Experience in analog and real number modeling preferred **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Skyworks (Cedar Rapids, IA)
- …Skills + BS & 5+ yrs (MS & 3+ yrs) experience in integrated circuit design / verification required + Expert in SystemVerilog and HDL programming languages + ... will include but not be limited to creating generalized SystemVerilog UVM testbenches with full functionality coverage...new verification tools to be used by verification / design teams + Work with design… more
- Meta (Austin, TX)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Austin, TX)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
- Meta (Austin, TX)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs,...14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more
- Northrop Grumman (Annapolis Junction, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
- Qualcomm (Santa Clara, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... related field + 2+ years of experience with ASIC design and verification tools, techniques, and methodology...and methodology + 3+ years of experience with digital design concepts and RTL languages such as SystemVerilog… more
- Amazon (Boise, ID)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Google (Sunnyvale, CA)
- …logic at RTL using SystemVerilog for ASICs. + Experience in memory subsystem design verification . + Experience in Power aware verification , Gate level ... engineers to identify important verification scenarios. + Create a constrained-random verification environment using SystemVerilog and UVM . + Identify… more
- Meta (Sunnyvale, CA)
- …verification . 10. 10+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a… more
- Meta (Redmond, WA)
- …joining Meta 8. Experience with ASIC development cycle. 9. Experience in Verilog, SystemVerilog , C/C++ based verification and UVM methodology. 10. Experience ... the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with… more
- Qualcomm (San Diego, CA)
- … design team. + Architect and develop the testbench using advanced verification methodology such as SystemVerilog / UVM , Analog/mixed signal simulation, Low ... Group, Engineering Group > ASICS Engineering **General Summary:** Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP… more
- Capgemini (Seattle, WA)
- …Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in design ... the Job You're Considering** We are seeking a SoC Design Verification Engineer to join our team...+ 8 to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in… more
- Google (Madison, WI)
- … scenarios. + Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM ). + Identify ... degree or PhD in Electrical Engineering. + 6 years of experience in design verification . + Experience with industry-standard simulators, revision control systems… more
- Google (Mountain View, CA)
- …scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or formally ... digital Intellectual Property (IP) and subsystems. + Experience in Design Verification (DV) Testbenches/Environments. Preferred qualifications: + Master's… more
- Siemens (Austin, TX)
- …800G, 1.6T, UEC and beyond . + Develop scalable VIP frameworks leveraging UVM (Universal Verification Methodology), SystemVerilog , and formal verification ... expertise in Ethernet technology and a strong focus on design verification . In this role, you...and networking protocols . + Strong hands-on experience with SystemVerilog , UVM , and scripting languages (Python, TCL,… more
- Amazon (Sunnyvale, CA)
- …or CS - 7 years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven ... Description As a Senior Design Verification (DV) Engineer, you will... engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM… more