- SpaceX (Sunnyvale, CA)
- Sr. ASIC / SOC DFT Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC / SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- SpaceX (Sunnyvale, CA)
- SOC / ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... the ultimate goal of enabling human life on Mars. SOC / ASIC SYNTHESIS & FRONT-END STA ENGINEER...Work closely with chip architecture, design verification, physical design, DFT , and power teams to achieve tapeout success on… more
- Qualcomm (Santa Clara, CA)
- …on time with high quality + Responsible for deliverables of certain aspects of SoC DFT execution + Responsible for pattern verification and debug Although this ... Minimum of 3+ years experience in the area of ASIC / DFT + In depth knowledge of ...propose best compression that can be achieved for given SoC /core/block + Own and deliver scan insertion, validate equivalence… more
- Amazon (Sunnyvale, CA)
- …(Perl/Tcl) - Experience in bringing up ATE test programs and taking complex SOC / ASIC to production. - Experience in leading DFT teams and test engineers in ... generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on...backend, test, reliability and more. As part of the SOC DFT team, you will: - Lead… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on the world of technology. Looking for Lead SoC / ASIC Digital Design Engineer with experience in Design for Test ( DFT ). Ability to lead from DFT ... Requirements; + Prior 15-20 years of professional experience in SoC / ASIC Digital Design with focus on Design for Test ( DFT ) + Should be able to lead DFT … more
- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a DFT Engineer you will work with chip architects, chip designers, ... design; experience using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 5+...Mentor Tessent tools + Experience with defining and implementing SOC level verification on large designs. + Experience in… more
- Meta (Sunnyvale, CA)
- …( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....with the Designers to create waivers. 5. Perform RTL DFT Analysis and improve the DFT coverage… more
- SpaceX (Sunnyvale, CA)
- Sr. ASIC Design Engineer , DDR IP (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER , DDR IP (SILICON ENGINEERING)...quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects… more
- Siemens Digital Industries Software (Fremont, CA)
- …* Normal office environment. * Experience with design, simulation, verification of ASIC /VLSI/ SoC circuits and systems, design verification and product test ... 6 to 15 years of experience as an Applications Engineer or related field * Digital design experience and...* Proven track record of Design for Test for ASIC design. * Demonstrated knowledge of Tcl language and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... plans for NVIDIA's next generation of CPU, GPU or SOC designs. + Owning STA of large subsystems and...MS (or equivalent experience) with 2+ years experience in ASIC Design and Timing + Great understanding of timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Engineer . NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC 's ... Engineering or Computer Engineering. + 3+ years of experience working on ASIC design and development. + Experience in micro-architecture and RTL development of… more
- NVIDIA (Santa Clara, CA)
- … ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working engineers to craft and implement ... high quality release of the Memory Controller IP for SoC design, as per schedule. You will responsible for...+ BS, MS, or PhD in Electrical Engineering, Computer Engineer , or related degree required (or equivalent experience). +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... years' experience or MS (or equivalent experience) with 2+ years' experience in ASIC Design and Timing + Great understanding of timing and physical design… more
- Google (Sunnyvale, CA)
- …emulation, FPGA validation and debug, functional verification, physical design, and DFT methodologies. + Experience with SOC implementation standards and ... that power all of Google's services. As a Hardware Engineer , you design and build the systems that are...the planning, creation, and delivery of top-level RTL/deliverables for ASIC and SOC projects from concept to… more
- SpaceX (Sunnyvale, CA)
- …make this possible, with the ultimate goal of enabling human life on Mars. SOC / ASIC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING) At SpaceX we're ... SOC Physical Design STA/Timing Engineer (Silicon...physical design flow + Work with systems and architecture, SOC integration, verification, DFT , mixed signal, IP… more
- Amazon (Sunnyvale, CA)
- …STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification, DFT , Mixed Signal, IP owners, Synthesis, Place & Route ... Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our...STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. - Full chip timing constraints development, full chip… more
- Google (Sunnyvale, CA)
- …experience. + 5 years of experience in test engineering or product engineering. + Experience in ASIC or SoC DFT test development, bring-up, or debug for NPI ... the next generations of chips. You'll help to integrate SoC technologies into devices and drive ATE manufacturing testing...expertise to drive quality improvements. + Collaborate with design, DFT , and quality teams to drive best practices for… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems. Qualcomm ... of Qualcomm Connectivity organization responsible for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state… more
- Google (Mountain View, CA)
- …+ Knowledge of high performance and low-power design techniques. + Knowledge of ASIC verification, design for testing ( DFT ), or physical design. + Knowledge ... that power all of Google's services. As a Hardware Engineer , you design and build the systems that are...quality checks. + Work with cross-functional teams such as SOC integration, DFT and Physical design to… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Product Development Engineer to join our outstanding Automotive/Embedded Products team! As part of an Operations Engineering team ... implement test processes to improve manufacturing efficiency for our latest SOC /CPU/iGPU architectures, built in leading-edge process technology + Analyze product… more