• CPU DFT Engineer

    Qualcomm (Santa Clara, CA)
    …Group, Engineering Group > CPU Engineering **General Summary:** As a DFT Engineer you will work with chip architects, chip designers, implementation ... engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and...using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 5+ years of practical experience… more
    Qualcomm (04/17/24)
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  • Senior Physical Design and Timing Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... and ECO implementation. + Work in a cross-functional environment interacting with multiple teams. + Apply knowledge and experience to improve the convergence flows… more
    NVIDIA (03/07/24)
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  • Senior ASIC Engineer , Timing

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... generation and implementation. + Work in a cross-functional environment interacting with multiple teams. + Work on project execution as well as methodology… more
    NVIDIA (04/18/24)
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