- Integense (Portland, OR)
- …STA, PnR, DFT and ATPG, extraction, etc. + Experience with pre-silicon RTL design verification , System Verilog or UVM /OVM/VMM, test bench creation, ... designs for best in class ATE products. Responsibilities: + Complete Ownership of the Digital Design and Verification for ATE products - full Front End and Back… more
- SpaceX (Irvine, CA)
- …and tools (Veloce, Palladium, Zebu, and/or proFPGA, Protium, HAPS) + Experience with design verification and SystemVerilog, UVM , and C/C++ verification ... computer engineering or computer science + 2+ years of experience with design verification or emulation PREFERRED SKILLS AND EXPERIENCE: + Experience… more
- Actalent (Berkeley, MO)
- …requirements. Additional Skills & Qualifications: Qualifications: o Extensive experience in both formal design and formal UVM verification roles o Experience ... Description: Responsibilities: o Own requirements based verification and qualification of FPGA (own the VCRM)...the VCRM) o Review designs and collaborate with multiple verification sub-teams to ensure complete, robust verification … more
- NVIDIA (Santa Clara, CA)
- …in Computer or Electrical Engineering (or equivalent experience). + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... automation, RTL integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and automation… more
- NVIDIA (Hillsboro, OR)
- … automation + Excellent analytical and problem-solving skills + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... We are now looking for a CPU Design Methodology Engineer: The complexity of chip development...a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly.… more
- Microsoft Corporation (Mountain View, CA)
- …and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology ( UVM ) components to interface between test code and ... cloud servers, clients, and augmented reality. We are looking for a **Senior Design Verification Engineer** to work on leading-edge Intellectual Property (IP)… more
- Microsoft Corporation (Mountain View, CA)
- …and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology ( UVM ) components to interface between test code and ... extremely efficient manner. We are looking for a **Principal Design Verification Engineer** to work in the...of verification and debug principles, testbenches, Universal Verification Methodology ( UVM ) or C based test… more
- Microsoft Corporation (San Francisco, CA)
- …and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology ( UVM ) components to interface between test code and ... and augmented reality. We are looking for a **Principal Design Verification Engineer** to work in the...debugging failures and coverage signoff in C++ and Universal Verification Methodology ( UVM ). + 9+ years of… more
- Microsoft Corporation (Redmond, WA)
- …and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology ( UVM ) components to interface between test code and ... reality. We are looking for a **Senior Director- Principal Design Verification ** to work in the dynamic...debugging failures and coverage signoff in C++ and Universal Verification Methodology ( UVM ) + 10+ years of… more
- Textron (Hunt Valley, MD)
- …and verification skills with Test Bench experience + Experience with OVM/ UVM design verification methodology + Demonstrated software documentation ... used in the future products\. * Conduct prototype testing, integration testing, and design verification and validation testing * Document design , analysis,… more
- PDS Defense (Littleton, CO)
- … verification plan for a given design . -Use SystemVerilog and Universal Verification Methodology ( UVM ) to verify a design in a Linux-based ... **Engineering** **FPGA Design / Verification Engineer - Job ID#205553** Littleton,... of FPGA and/or ASIC devices. -Experience with modern verification methodologies such as UVM /OVM -Experience in… more
- Cadence Design Systems, Inc. (Austin, TX)
- …and assertion-based verification methodologies + Exposure to design and verification tools, and methodologies ( UVM or equivalent) + Define and implement ... based on verification test plan + Drive Design Verification to closure based on defined...the industry + 15+ years of hands-on experience in SystemVerilog/ UVM methodology and/or C/C++ based verification +… more
- Siemens Digital Industries Software (Wilsonville, OR)
- …Engineering from an accredited institution + Minimum of 2+ years of Digital Design / Verification experience + Knowledge of VHDL or Verilog, or SystemVerilog RTL ... management skills **Preferred qualifications:** + MS Electronic/Computer Engineering + Knowledge of UVM and System Verilog for Verification + Working knowledge… more
- Butler America (Littleton, CO)
- … verification plan for a given design . Use SystemVerilog and Universal Verification Methodology ( UVM ) to verify a design in a Linux-based ... FPGA Design / Verification Engineer Location: Littleton, CO Job... of FPGA and/or ASIC devices. *Experience with modern verification methodologies such as UVM /OVM *Experience in… more
- Amazon (Cupertino, CA)
- …locations: Cupertino, CA, USA Basic Qualifications - 5+ years of design verification experience using System Verilog and UVM - 5+ years of experience ... in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms.… more
- Amazon (Cupertino, CA)
- …TX, USA | Cupertino, CA, USA Basic Qualifications - 4+ years of design verification experience using System Verilog and UVM - 4+ years of experience in ... in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms.… more
- Actalent (Mountain View, CA)
- …AI into our development process. Candidate Requirements - Experience in design verification - Hands-on experience with UVM Testbench Test case coding - ... Description: FPGA Design Verification Simulation Testbench Creation Filing...of Experience 1. Minimum 10 YOE: Design Verification work 2. Minimum 5 YOE: UVM … more
- Actalent (Berkeley, MO)
- …the overall design and requirements. Top Skills: + FPGA Design + UVM + VCRM + Verification + Xilinx Additional Skills & Qualifications: Qualifications: + ... Remote Sr. FPGA Systems Engineer! Description: Responsibilities: + Own requirements based verification and qualification of FPGA (own the VCRM) + Collaborate with… more
- Actalent (Mountain View, CA)
- …Candidate Requirements + 10 overall years of experience in the design verification + Hands-on experience with UVM Testbench Test case coding + Working ... + The purpose of this team is : FPGA Design Verification Simulation Testbench Creation Filing bugs... work + Minimum 5 years of experience : UVM Testbech development and debugging + Minimum 5 years… more
- KBR (Columbus, OH)
- …for assurance analysis + Develop assurance metrics for analysis for a workflow emulated design + Learn basic UVM verification methodology and class libraries ... and presentation skills based on the literature research and results from simulating/emulating/ verification /malware detection in our chip design . As a National… more