- Qualcomm (San Jose, CA)
- …currently seeking candidates who will be responsible for the implementation and verification of DFT /DFD ( Design for Test/ Design for Debug) techniques for low ... designs. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT… more
- Microsoft Corporation (Mountain View, CA)
- …to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Front End Design Methodology Engineer to work in the ... Chip (AISoC) Silicon team. As the Front End Methodology Engineer , you will be responsible for developing and maintaining...be interacting with various teams, including architecture, front end design , verification, design for testing( DFT… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, Low Power, ... field, plus 8+ years industry experience. Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Prior… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Principal Physical Design Engineer ** to work on industry-leading, high-speed, ... team requirements. + Being responsible for all aspects of physical design including floorplanning, bump and ESD planning, synthesis, place-and-route, clock tree… more
- Microsoft Corporation (Mountain View, CA)
- …most ambitious chips in the industry. The Physical Design team is looking for Principal Static Timing Analysis (STA) Engineer to join us as we continue to ... and methodology. Our responsibilities span the complete spectrum including Design for Testability ( DFT ), full Register Transfer...we'd love to hear from you! **Responsibilities** As a Principal Static Timing Analysis (STA) Engineer , you… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, ... and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts...the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, ... Provide technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …experience + Experience working with DDR5/4, LPDDR5/4 IP. + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end ... experience is a plus + Familiarity with industry standard DFT flows and test methodologies. + Familiarity with package...and test methodologies. + Familiarity with package and board design . + Ability to read schematics and participate in… more
- Integense (San Jose, CA)
- …solutions to our customers. We are expanding and looking for a Senior / Principal Member of Technical Staff, Digital Design . This is an exciting opportunity ... by applying a holistic system-level approach combined with creative circuit design , proprietary silicon process technology and materials engineering, to provide… more
- Qualcomm (San Jose, CA)
- …locally and globally. Additional Competencies: + Experience in areas of memory diagnostics, design , DFT , or post-silicon debug. + Strong data analysis skills in ... this role, you will be a member of a global technical team working with Design , Process, Product, Test, and Failure Analysis teams, as well as EDA Software vendors.… more