- Qualcomm (Santa Clara, CA)
- …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the ... of timing closure, clock tree synthesis, power optimization, and physical verification methodologies. Additionally, communication skills and the ability to work in… more
- Microsoft Corporation (Sunnyvale, CA)
- …Computing Development Team is seeking passionate, driven, and intellectually curious ** Principal System On Chip Integration Engineer ** to deliver premium-quality ... represent a variety of disciplines including, but not limited to, design, verification , performance modeling and DevOps supporting the development of custom silicon.… more
- Microsoft Corporation (Mountain View, CA)
- …high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Front End Design Methodology Engineer to work in the dynamic ... End RTL methodologies for multiple SOCs + Thorough understanding of end-to-end SOC design cycles and dependencies between design, verification , physical design,… more
- Capgemini (San Jose, CA)
- …their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors ... during the interview process and that image may be used for verification , including during the hiring and onboarding process. Applicants for employment in… more
- Microsoft Corporation (Mountain View, CA)
- …cloud servers, clients, and augmented reality. We are looking for a ** Principal Physical Design Engineer ** to work on industry-leading, high-speed, mixed-signal ... signoff for timing, electromigration & voltage drop, and physical verification . + Integrating complex analog IPs within a digital...system. + Being a key interface between IP and SoC . + Working with packaging engineers to understand IP… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …detailed product definitions and test/release plans for every Cadence product. POSITION DETAILS Principal Firmware Engineer (T4) This is an opportunity to join a ... you think about and use IP in your system-on-chip ( SoC ) designs. As you use more IP to fortify...portfolio and many industry firsts in design IP and verification IP. Engineers choose Cadence when they want the… more
- Microsoft Corporation (Mountain View, CA)
- …the best and brightest to join us in designing for the future! As a ** Principal Engineer , DFT (Design for Testability)** in the Silicon Engineering and Solutions ... a variety of disciplines including, but not limited to, design, verification , performance modeling, and DevOps supporting the development of custom silicon.… more
- Micron Technology, Inc. (San Jose, CA)
- …technology while rapidly growing your abilities. **What's Encouraged Daily** As a Principal Firmware Engineer at Micron Technology, Inc., you will build ... Solid State Drives (SSD) that will improve performance, while reducing power, latency and SoC (System on Chip) complexity for the target sectors. You can expect to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and provide professional guidance to customers. + Support DDR PHY and controller SOC integration reviews, and integration questions. + Perform and help debug RTL and ... working with DDR5/4, LPDDR5/4 IP. + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end experience is a plus +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …customers working on advanced SOC and System designs Position The Virtual Protocol Principal Product Engineer has the opportunity to be an expert in many ... impact on the world of technology. This Lead Emulation Engineer position is with the Virtual Protocols Product Engineering...products to enable the critical shift-left of System Level SOC verification and Validation for Cadence customers.… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, validate, ... implement, and document IP (block/ SoC ) development for a variety of high performance, high...the area and power targets . Working with the verification engineers to develop unit-level and integrated-level test-benches .… more
- Qualcomm (San Jose, CA)
- …on time with high quality + Responsible for deliverables of certain aspects of SoC DFT execution + Responsible for pattern verification and debug Although this ... candidates who will be responsible for the implementation and verification of DFT/DFD (Design for Test/Design for Debug) techniques...and team work skills and good English is required ** Principal Duties & Responsibilities:** + The person hired in… more