- Techtronic Industries North America, Inc. (Brookfield, WI)
- …as well as weight, size, and cost optimizations. + Conduct linear and non-linear static analysis , modal analysis , frequency response, deflection analysis ... Principal Simulation & Analysis Engineer **Job...a variety of customers- must be strong in prioritization, timing , and scope discussions. + Grow organizational capability through… more
- Cadence Design Systems, Inc. (San Jose, CA)
- … analysis , place and route, extraction, spice etc. Job Responsibilities: . Perform Static timing analysis , glitch, noise analysis , extraction using ... related field of VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows,… more
- BAE Systems (Nashua, NH)
- …analyzer (ILA/chipscope/signaltap) + Digital simulation using Modelsim/Questa + Significant experience with static timing analysis and clock domain crossing ... **Job Description** BAE Systems is seeking a Senior Principal FPGA Design Engineer! See what you re...architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing and… more
- BAE Systems (Totowa, NJ)
- …Vivado or Intel/Altera Quartus Digital simulation using Modelsim/Questa Significant experience with static timing analysis and clock domain crossing ... **Job Description** BAE Systems is seeking a Principal FPGA Design Engineer! See what you re...architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing and… more
- onsemi (Richardson, TX)
- …design concept to chip tape-out. Tasks include: + Verilog RTL coding + Design-for-Test + Static Timing Analysis in a variety of technologies + Logical and/or ... physical synthesis + UPF creation and low-power design + Analysis and design of complex timing and clock interfaces + IP integration, including analog content… more
- Northrop Grumman (Dulles, VA)
- …FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis , and power analysis + Experience ... . In this role, you will be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and… more
- Micron Technology, Inc. (Boise, ID)
- …signal integrity, differential and single-ended interface technologies. + Deep understanding of timing budgets and jitter analysis . + Expertise in Printed ... Signal &Power Integrity team under HSE group, as a Principal Signal Integrity Engineer at Micron, we are responsible...we are responsible for: + Leading the design and analysis of high speed memory interfaces and power distribution… more
- Cadence Design Systems, Inc. (Cary, NC)
- …the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc. - Deep experience of static timing analysis - Ability to learn quickly - High level ... who want to make an impact on the world of technology. Principal Physical Design Engineer (PNR/Physical Verification/STA/EMIR) The candidate will have the… more
- Microsoft Corporation (Santa Clara, CA)
- …of low power microarchitecture techniques. knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis Silicon Engineering IC5 - The typical ... team within the Azure Hardware Systems & Infrastructure group is seeking a Principal Silicon Engineer. You will join our front-end silicon team and be responsible… more
- Microsoft Corporation (Santa Clara, CA)
- …of low power microarchitecture techniques. Knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis + Self-motivated and able to work ... team within the Azure Hardware Systems & Infrastructure group is seeking a Principal Silicon Engineer. You will join our front-end silicon team and be responsible… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to success + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best...tools including Place and Route, IR Drop, backend design timing and power closure + Experience with advanced nodes… more
- Cadence Design Systems, Inc. (Austin, TX)
- …design/EDA experienceStrong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is requiredPrior experience with ... Design Implementation and Signoff including Place and Route, Design Closure, and timing /power signoffGuide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (Austin, TX)
- …Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR , CTS, Static Timing Analysis ) experience and knowledge are required * Innovate ... to make an impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip… more
- Micron Technology, Inc. (Minneapolis, MN)
- …optimization of Memory/Logic/Analog circuits. + Chip floor-planning, physical design, IP integration, static timing analysis , design validation, and required ... collaborative skills in this exciting and outstanding opportunity. We're looking for a Principal Physical Design Engineer (ASIC) to join our team! You will be… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …industry experience. Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Prior experience ... Preferred Good hands-on experience of Floorplanning , Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite Prior experience with… more
- Cadence Design Systems, Inc. (Austin, TX)
- …design/EDA experience Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required Prior experience ... backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure Experience in scripting languages such as Tcl/Perl/Python is… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding of ... fundamental physical design flows and stages + Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. + Exhibit excellent communication skills and be self-motivated and well organized. + Experience with… more
- Micron Technology, Inc. (Folsom, CA)
- …of HBM JEDEC protocol + Experience with RTL (Verilog, System Verilog) + Experience with static timing analysis The US base salary range that Micron ... to entire department. + Participate in continuing education and competitor analysis . + Proactively solicit feedback from Standards, CAD, modeling, and verification… more
- Micron Technology, Inc. (Atlanta, GA)
- …a team + Experience with IP design/architecture + Knowledge of Verilog and static timing analysis + Excellent problem-solving and analytical skills ... + A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds + Having an innovative approach that is open to improving upon any of our processes or products. The US base salary range that Micron Technology estimates it… more
- Qualcomm (San Diego, CA)
- …Develop constraints for physical power aware synthesis, low power multi voltage domain checks, static timing analysis and power aware formal verification. + ... team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis , STA and CLP for premium tier chips. This is… more