- NVIDIA (Santa Clara, CA)
- …team and see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. ... verification methodologies. + Contribute to architecting and developing brand-new RTL analysis flows. + Serve as an...documents and train internal users. + Use data collection, analysis , and reporting tools to provide methodology … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... digital implementation tools + Working closely with R&D on tools and methodology improvements + Create and contribute technical content for Cadence Online Support… more
- Qualcomm (Austin, TX)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with implementation and CAD teams to ... experience + Experience with Synthesis, place and route and signoff timing/power analysis . + Knowledge of high performance and low power implementation techniques +… more
- Google (Sunnyvale, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the world's ... (https://careers.google.com/benefits/) . + Develop, support, and execute implementation flows from RTL through GDS including some or all of the following: synthesis,… more
- Qualcomm (Austin, TX)
- …+ Knowledge of scripting languages like TCL and Python. + Familiarity with power analysis and optimization methods + Familiarity with the entire RTL2GDS flow ( RTL ... , equivalence, synthesis, PnR) and intent checking + Strong communication skills are required as you will interact with a lot of different groups + Entry level or Experienced **Minimum Qualifications:** * Bachelor's degree in Electrical Engineering, Computer… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Power Optimization and Analysis Engineer ! NVIDIA prides ourselves in having energy efficient products. We believe that continuing ... NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate...internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve… more
- Meta (Austin, TX)
- …with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System ... Perform RTL Lint and work with the Designers to create waivers. 5. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 6. Perform Flat… more
- Microsoft Corporation (Raleigh, NC)
- …will: + Establish Logical Equivalence Checking (LEC)/Formal Equivalence Verification (FEV) methodology for hierarchical and block-level partitions between RTL , ... and have a keen interest in driving the associated methodology for large and intricate digital System on Chip...CAD (Computer Aided Design) flow systems + Perform detailed debug/ analysis to guide the RTL and physical… more
- Renesas (Edinburgh, IN)
- …& chip-level verification techniques + Strong & proven ability to debug both RTL & gate-level simulations + Experience with methodology and flow automation ... Principal Digital Design Engineer Job Description We are actively seeking an...budget schedule and project deliverable goals + Designing digital RTL that meets timing, area, power and any adhering… more
- SpaceX (Sunnyvale, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX...teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +… more
- Microsoft Corporation (Raleigh, NC)
- …Design) , Design Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis, RTL Power Analysis , Physical Design ( PD) Handoff and System on ... Solutions Team is looking to hire a **Senior Silicon Engineer ** to join our Central Front-End Tools, Flows and...** to join our Central Front-End Tools, Flows and Methodology (TFM **)** group. This team drives state-of-the-art converged… more
- Qualcomm (San Diego, CA)
- …responsible for development of next Generation, high performance, low power Memory Subsystem RTL Design, flows and methodology for high performance ASICs in ... performance ASIC designs, and, ability to execute critical power analysis of critical design IPs for path to DDR....next generation memory subsystem micro architecture, and get to rtl code, use advanced asic design flows to ensure… more
- Microsoft Corporation (Mountain View, CA)
- …chips in the industry. The Physical Design team is looking for Principal Static Timing Analysis (STA) Engineer to join us as we continue to build a world-class ... team and methodology . Our responsibilities span the complete spectrum including Design...hear from you! **Responsibilities** As a Principal Static Timing Analysis (STA) Engineer , you will be responsible… more
- Siemens Digital Industries Software (San Diego, CA)
- …responsible for technical selling and support of PowerPro, a leading-edge platform for RTL /gate Power analysis and optimization. This includes, but is not ... required. Job Qualifications *5+ years of industry experience as an Applications Engineer or related field. *Proven hands-on ASIC RTL VHDL/Verilog/SystemVerilog… more
- Northrop Grumman (Linthicum, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug **Senior Principal Engineer Basic Qualifications:** + Bachelor's ... tools and techniques. The individual will perform functional verification of register transfer level ( RTL ) code of a complex ASIC at block level and SOC level using… more
- Northrop Grumman (Linthicum, MD)
- …tools and techniques. The individual will perform functional verification of register transfer level ( RTL ) code of a complex ASIC at block level and SOC level using ... UVM (Universal Verification Methodology ) and SystemVerilog and Cadence Xcelium simulation tool. This...and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc. This candidate… more
- ManpowerGroup (San Jose, CA)
- …need:** + A minimum of 3 years of experience with STA (Static Timing Analysis ) and PrimeTime and related timing constraints methodology and SDC constraints ... time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can help along...language + A minimum of 3 years of experience RTL Integration, 3 rd Party IP RTL … more
- Qualcomm (San Diego, CA)
- …on QUALCOMMs Adreno Graphics cores in the area of Low Power implementation and methodology . The Power Implementation Engineer will work in QUALCOMMs Adreno GPU ... will have responsibilities in one or more of the following areas: Power Analysis and Estimation, RTL and Synthesis Power Minimization, Power Intent design… more
- Cadence Design Systems, Inc. (Austin, TX)
- …with leading edge Wireless and Mobile Customers * Senior level Application Engineer position supporting RTL -to-GDS implementation flows using Encounter Digitial ... impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... NVIDIA's designs + Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and circuits design, and timing and power convergence… more