• RTL Digital Design

    Cadence Design Systems, Inc. (San Jose, CA)
    …Responsibilities Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, ... or related field, plus 8+ years industry experience. Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is… more
    Cadence Design Systems, Inc. (03/07/24)
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  • RTL Senior Principal Digital

    Cadence Design Systems, Inc. (San Jose, CA)
    …is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP integration and ... front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will… more
    Cadence Design Systems, Inc. (03/01/24)
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  • Senior RTL to GDS Principal

    Cadence Design Systems, Inc. (San Jose, CA)
    …Responsibilities Provide technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, ... degree Computer Science/Engineering, Electrical, Engineering, or related field8+ years of design /EDA experienceStrong knowledge in Digital Design more
    Cadence Design Systems, Inc. (04/27/24)
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  • CPU Micro-architect/ RTL Designer

    Qualcomm (Santa Clara, CA)
    …the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As ... a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm… more
    Qualcomm (04/10/24)
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  • Senior Principal ASIC Design

    BAE Systems (San Jose, CA)
    …Systems. We are seeking a very senior level engineer to: + Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from concept to production. + ... incentives may be available based on position level and/or job specifics. **Senior Principal ASIC Design Engineer (Hybrid)** **95186BR** EEO Career Site Equal… more
    BAE Systems (04/13/24)
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  • Senior Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …product. Responsibilities include hardware architecture and micro-architecture definition, as well as RTL design to achieve high performance and low power. ... an impact on the world of technology. Successful applicant will participate in the design and development of a fully configurable and fully featured Network on Chip… more
    Cadence Design Systems, Inc. (04/11/24)
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  • Digital Design Engineer (Staff)

    Qualcomm (Santa Clara, CA)
    …future for all. As a Qualcomm ASIC Engineer, you will define, model, design ( digital and/or analog), optimize, verify, validate, implement, and document IP ... * Leverages advanced ASIC knowledge and experience to define, model, design ( digital and/or analog), optimize, verify, validate, implement, and… more
    Qualcomm (04/20/24)
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  • Sr. Digital Design Engineer

    Integense (San Jose, CA)
    …expanding and looking for a Senior / Principal Member of Technical Staff, Digital Design . This is an exciting opportunity to join the company early enough ... what matters. A true expert in all aspects of digital design , you enjoy problem-solving and balancing...Experienced in all Front and Back End activities - RTL , Verification, Synthesis, STA, DFT, ATPG, etc. + Adept… more
    Integense (03/27/24)
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  • Principal Silicon Validation Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …years of overall experience + Experience working with DDR5/4, LPDDR5/4 IP. + Verilog RTL design and gate level verification experience. + Synthesis and STA ... and help lead the development of best in class digital and mixed signal IP products. This is a...reviews, and integration questions. + Perform and help debug RTL and gate level simulations to verify functionality. +… more
    Cadence Design Systems, Inc. (03/01/24)
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  • Senior Physical Design Applications…

    Cadence Design Systems, Inc. (San Jose, CA)
    …4 years of experience. Master's degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is ... to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales...digital implementation flows and EDA tools is required, RTL to GDSII ; Experience with advanced nodes (7nm… more
    Cadence Design Systems, Inc. (04/13/24)
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  • Mobile Chipset Engineer

    Qualcomm (Santa Clara, CA)
    …future for all. As a Qualcomm ASIC Engineer, you will define, model, design ( digital and/or analog), optimize, verify, validate, implement, and document IP ... * Leverages advanced ASIC knowledge and experience to define, model, design ( digital and/or analog), optimize, verify, validate, implement, and… more
    Qualcomm (05/11/24)
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  • Mixed Signal IP - Senior Program Manager

    Cadence Design Systems, Inc. (San Jose, CA)
    …of end-to-end design flow and tools for both analog and digital design from Architecture (schematics and RTL ) to GDS + MSEE preferred Key competencies + ... make an impact on the world of technology. Senior Principal Program Manager We are looking for a Senior...R&D Development Projects and Key Customer Engagements within the Design IP Group. The candidate must have solid, hands-on… more
    Cadence Design Systems, Inc. (02/27/24)
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  • Senior DFT Engineer

    Qualcomm (San Jose, CA)
    …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will ... be responsible for the implementation and verification of DFT/DFD ( Design for Test/ Design for Debug) techniques for...Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like… more
    Qualcomm (04/18/24)
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