• Staff SOC Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the development and ... processes, and an understanding of timing closure, clock tree synthesis , power optimization, and physical verification methodologies. Additionally, communication… more
    Qualcomm (04/12/24)
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  • Sr. SOC Design Engineer - STA, Hardware…

    Amazon (Sunnyvale, CA)
    …and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis , Place & Route and other local/remote teams to address the design ... - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. - Full chip timing constraints development, full chip / Sub-System STA and… more
    Amazon (02/20/24)
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  • Principal Products & Systems Engineer

    Capgemini (Santa Clara, CA)
    …a visa for employment authorization in the US by Capgemini. **Director Custom ASIC Programs, RTL to GDSII - Solutions Architect** **Summary** Person will be ... on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for… more
    Capgemini (03/28/24)
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  • Design Engineer, Custom Circuits

    Google (Sunnyvale, CA)
    …hardware architecture leads to overcome the slowing of Moore's Law and deliver cutting edge ASIC 's and SoC 's. You will work on topics that span circuit design, ... IR analysis. + Understanding of design kit collaterals for front end and back end design teams. + Familiarity...a leading edge technology platform for custom, high performance ASIC 's and SoC 's, from design through manufacturing,… more
    Google (03/19/24)
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