We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and...ASIC design including RTL and logic design , physical and circuits design ,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and … more
- Amazon (Sunnyvale, CA)
- Description As a Sr. ASIC Design Engineer, you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop ... IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional...registers, and error handling. - Experience working closely with physical design teams to develop highly optimized… more
- SpaceX (Sunnyvale, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... Sr. FPGA/ ASIC Design Engineer (Silicon Engineering) at...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
- NVIDIA (Santa Clara, CA)
- …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...SOC clocking. The team collaborates with the front end design team to understand the clocking requirements for the… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... Sr. ASIC Design Engineer, DDR IP (Silicon...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
- SpaceX (Sunnyvale, CA)
- Sr. ASIC Design Verification Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- … Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or ... We are now looking for a motivated Senior ASIC Engineer, Timing to join...intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,… more
- NVIDIA (Santa Clara, CA)
- … Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...of RTL/logic design skills as well as physical design /circuit skills for timing closure. +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- NVIDIA (Santa Clara, CA)
- … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis… more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Master's degree in Science, Engineering, or related field and 3+ years of ASIC design , verification, validation, integration, or related work experience. OR PhD… more
- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the development and ... products at Qualcomm. This role requires strong knowledge of physical design tools (like Cadence or Synopsys),...Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...expertise is required as is a deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …the opportunity to build complex GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design , CAD, Package Design , Software, DFT and ... NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design...design quality checks and reviews to present the physical design team with high-quality RTL What… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …The Position Requirements are + Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4 years of experience. Master's ... degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is...Static Timing Analysis is required + Prior experience with ASIC digital implementation flows and EDA tools is required,… more
- NVIDIA (Santa Clara, CA)
- …software design , algorithms, data structures, testing + Familiarity with Verilog and ASIC and physical design along with experience in commercial EDA ... you a software engineer with a passion for hardware, ASIC design and VLSI? Be part of... software including RTL synthesis, equivalence checking, and early physical design and methodology for all of… more
- Qualcomm (San Jose, CA)
- …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will be ... Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR… more
- NVIDIA (Santa Clara, CA)
- … Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing ... team of Photonics, CMOS, Electronics, and Systems engineers + Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits,… more
- NVIDIA (Santa Clara, CA)
- … Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic ... high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog… more