• Senior Software Engineer, Server…

    NVIDIA (Santa Clara, CA)
    …correction codes (ECC), and error recovery mechanisms. + Proficiency in system-level simulation tools and methodologies (eg, fault injection, reliability ... experienced engineer having experience with RAS(Reliability, Availability, and Serviceability) and fault mode analysis (FMEA). You will be responsible for improving… more
    NVIDIA (02/27/24)
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  • Senior Data Analytics Engineer - DFT…

    NVIDIA (Santa Clara, CA)
    …Machine Learning or Database Management. + Understanding of fundamental DFT topics, such as, fault modeling, ATPG and fault simulation . + Experience in ... the choice to join us today. In this exciting Senior Data Analytics Engineer - DFT Methodology engineering role,...for improving our outgoing quality of chips including advanced fault modeling and Silicon Lifecycle Management. + You will… more
    NVIDIA (04/06/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation + Excellent analytical skills ... post-silicon lifecycle support. + Partner with the top EDA tool vendors to develop new capabilities to support NVIDIA...logic on complex and multi-million gate designs using vendor tools + Good exposure to multiple domains including RTL… more
    NVIDIA (04/12/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation + Excellent analytical skills ... of test patterns and logic on complex and multi-million gate designs using vendor tools + Good exposure to cross functional areas including RTL & clocks design, STA,… more
    NVIDIA (04/16/24)
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  • Senior Lead DFT Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …insertion flows + Basic scan chain insertion using synthesis or other software tools + Experience in compression scan insertion, LBIST and other scan technologies + ... goals + Debug and Analysis of failures to improve fault coverage + Verification of ATPG testbenches and debugging...Verification of ATPG testbenches and debugging root cause of simulation mis-compares + Working knowledge of JTAG 1149.1/6, IEEE1500… more
    Cadence Design Systems, Inc. (04/06/24)
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