- Novo Nordisk Inc. (Boulder, CO)
- …you ready to make a difference? The Position Novo Nordisk is seeking a Senior Scientist to join our RNAi Chemical Development group in Boulder, Colorado. You will ... enzymatic ligation of oligonucleotides, biocatalytic processes pertaining to RNA synthesis , bioconjugation, and transglycosylation of nucleosides. The successful candidate… more
- Novo Nordisk Inc. (Boulder, CO)
- …operation. Relationships The Technical Team Lead, API Manufacturing reports to the Senior Manager, API Manufacturing. The Technical Team Lead works with Chemical ... Technical Team Lead, API Manufacturing acts as a delegate for the Senior Manager API Manufacturing. Essential Functions Responsible for the manufacture of… more
- SpaceX (Sunnyvale, CA)
- …needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual level and base salary ... the Starlink network. RESPONSIBILITIES: + Full chip and block level timing constraint development, consistent full chip and block...timing validation flows + Execute low power design and physical synthesis , deploying knowledge of unified power… more
- PPL Corporation (Louisville, KY)
- …procedures under immediate guidance and instruction from Team Leader or more senior level Product Analysts. **_Intermediate Product Analyst_** : The Product ... moderate guidance and direction from Team Leader or more senior level Product Analysts. The Intermediate ...team to pull in relevant data and assisting in synthesis which the team can easily digest. 3. Serve… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Physical Design Engineer** to work on leading edge Intellectual Property ... have the opportunity to implement designs in Register Transfer Level (RTL) to Physical Design (PD) and...in hardware design. + 4+ years of experience in synthesis , timing constraints and timing closure, front-end design checks,… more
- NVIDIA (Santa Clara, CA)
- …on-chip interconnect network and last- level caches , working closely with the physical design team on implementation, synthesis and timing closure as well as ... experience in processor or other related high-performance semiconductor designs. + Physical design expertise including hands-on synthesis experience and in-depth… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPUs,...of high-frequency and low-power CPUs, GPUs, SoCs at block level , cluster level , and/or full chip … more
- NVIDIA (Santa Clara, CA)
- …experience) with 6+ years experience in Physical Design + Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to ... We are now looking for a motivated Senior ASIC Physical Design PPA (Performance,...design recommendations to address those + Familiarity with logic synthesis , equivalence checking, DFT, Floorplanning, Place & Route, and… more
- Microsoft Corporation (Raleigh, NC)
- …checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites within the Microsoft silicon engineering ... organization. We are looking for a ** Senior Silicon Engineer** to join our team! **Microsoft's mission is to empower every person and every organization on the… more
- Microsoft Corporation (Raleigh, NC)
- …VIP Design) , Design Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis , RTL Power Analysis, Physical Design ( PD) Handoff and ... Engineering and Solutions Team is looking to hire a ** Senior Silicon Engineer** to join our Central Front-End Tools,...area. + 4 + years of experience in Design Synthesis + 2+ years of demonstrated experience in one… more
- Microsoft Corporation (Mountain View, CA)
- …designs. + Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis , and System on Chip (SOC) ... functions in an extremely efficient manner. We are looking for a ** Senior Design Engineer** to work in the dynamic Microsoft Artificial Intelligence System… more
- Cadence Design Systems, Inc. (Austin, TX)
- …should include ASIC design using industry-standard hardware description languages (Verilog) * Senior Level Applications Engineer position with Deep Cadence or ... Synopsys place and route tool knowledge ( Physical Synthesis , PnR , CTS, Static Timing...working with leading edge Wireless and Mobile Customers * Senior level Application Engineer position supporting RTL-to-GDS… more
- NVIDIA (Westford, MA)
- …and/or full chip level . + Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. + Help in driving ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding...What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs… more
- Siemens Digital Industries Software (Fremont, CA)
- …of various functions of Aprisa Product line such as Placement, Clock Tree Synthesis , Optimization and Routing. Work on physical design activities for advanced ... 1. Working with advanced FinFet nodes from leading foundries 2. Working with physical design flows from placement, clock tree synthesis and routing; 3.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs...of high-frequency and low-power CPUs, GPUs, SoCs at block level , cluster level , and/or full chip … more
- Siemens Digital Industries Software (Waltham, MA)
- …Family:** Research & Development **Req ID:** 413362 Company: Siemens EDA Job Title: Senior Software Engineer Job Reference #: 413362 Job Location: Waltham MA Siemens ... circuit designs. In emulation systems, custom software compiles a circuit design's high- level description into a low level binary representation that can… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …3DIC. + Working with customers in one or more of the following areas: Synthesis , Place and Route, timing and power signoff. + Understanding and proliferating Cadence ... and compensation may vary based on factors such as qualifications, skill level , competencies and work location. Our benefits programs include: paid vacation and… more
- The Boeing Company (Huntington Beach, CA)
- …and qualifications, as well as market and business considerations. Summary pay range Senior Level 5: $145,350.00 - $210,450.00 Summary pay range Principal ... teams are currently hiring for a broad range of experience levels including; Senior or Principal Level Microelectronics Research & Development Investigators. We… more
- NVIDIA (Santa Clara, CA)
- …full chip designs or at block- level with additional responsibilities for block level synthesis /optimization + You will be responsible for all aspects of ... Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing...in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills… more
- The Boeing Company (El Segundo, CA)
- …Summary pay range for Lead Level : $128,350 - $215,500 Summary pay range for Senior Level : $153, 850 - $259,000 **Sign-On Bonuses** : New Hire Sign-On Bonus ... & Verification Team Lead Engineers at Experienced, Lead and Senior levels** **to join us as part of our...System Verilog, as well as experience with simulation and synthesis tools. + Familiarity with performance optimization and power… more
