- SpaceX (Sunnyvale, CA)
- …needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual level and base salary ... the Starlink network. RESPONSIBILITIES: + Full chip and block level timing constraint development, consistent full chip and block...timing validation flows + Execute low power design and physical synthesis , deploying knowledge of unified power… more
- PPL Corporation (Louisville, KY)
- …procedures under immediate guidance and instruction from Team Leader or more senior level Product Analysts. **_Intermediate Product Analyst_** : The Product ... moderate guidance and direction from Team Leader or more senior level Product Analysts. The Intermediate ...team to pull in relevant data and assisting in synthesis which the team can easily digest. 3. Serve… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Physical Design Engineer** to work on leading edge Intellectual Property ... have the opportunity to implement designs in Register Transfer Level (RTL) to Physical Design (PD) and...in hardware design. + 4+ years of experience in synthesis , timing constraints and timing closure, front-end design checks,… more
- NVIDIA (Santa Clara, CA)
- …on-chip interconnect network and last- level caches , working closely with the physical design team on implementation, synthesis and timing closure as well as ... experience in processor or other related high-performance semiconductor designs. + Physical design expertise including hands-on synthesis experience and in-depth… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPUs,...of high-frequency and low-power CPUs, GPUs, SoCs at block level , cluster level , and/or full chip … more
- Microsoft Corporation (Hillsboro, OR)
- …checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites within the Microsoft silicon engineering ... organization. We are looking for a ** Senior Silicon Engineer** to join our team! **Microsoft's mission is to empower every person and every organization on the… more
- NVIDIA (Santa Clara, CA)
- …experience) with 6+ years experience in Physical Design + Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to ... We are now looking for a motivated Senior ASIC Physical Design PPA (Performance,...design recommendations to address those + Familiarity with logic synthesis , equivalence checking, DFT, Floorplanning, Place & Route, and… more
- Microsoft Corporation (Raleigh, NC)
- …VIP Design) , Design Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis , RTL Power Analysis, Physical Design ( PD) Handoff and ... Engineering and Solutions Team is looking to hire a ** Senior Silicon Engineer** to join our Central Front-End Tools,...area. + 4 + years of experience in Design Synthesis + 2+ years of demonstrated experience in one… more
- The Boeing Company (Tukwila, WA)
- …$116,150 Summary pay range Mid- Level : $104,550 - $141,450 Summary pay range Senior Level : $126,650 - $171,350 Applications for this position will be accepted ... Currently SSED is actively hiring **Custom Integrated Circuit Design Engineers (Associate, Mid- Level , Senior ),** who have expertise and/or course work in… more
- Cadence Design Systems, Inc. (Austin, TX)
- …should include ASIC design using industry-standard hardware description languages (Verilog) * Senior Level Applications Engineer position with Deep Cadence or ... Synopsys place and route tool knowledge ( Physical Synthesis , PnR , CTS, Static Timing...working with leading edge Wireless and Mobile Customers * Senior level Application Engineer position supporting RTL-to-GDS… more
- Microsoft Corporation (Redmond, WA)
- …Development Team is seeking passionate, driven, and intellectually curious ** Senior System On Chip Integration Engineer** to deliver premium-quality designs ... and Intellectual Property (IP) Design Engineers to ensure Register Transfer Level (RTL) quality and timeliness. + Continuously evaluate and refine implementation… more
- NVIDIA (Westford, MA)
- …and/or full chip level . + Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. + Help in driving ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding...What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs… more
- Siemens Digital Industries Software (Fremont, CA)
- …of various functions of Aprisa Product line such as Placement, Clock Tree Synthesis , Optimization and Routing. Work on physical design activities for advanced ... 1. Working with advanced FinFet nodes from leading foundries 2. Working with physical design flows from placement, clock tree synthesis and routing; 3.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs...of high-frequency and low-power CPUs, GPUs, SoCs at block level , cluster level , and/or full chip … more
- Siemens Digital Industries Software (Waltham, MA)
- …Family:** Research & Development **Req ID:** 413362 Company: Siemens EDA Job Title: Senior Software Engineer Job Reference #: 413362 Job Location: Waltham MA Siemens ... circuit designs. In emulation systems, custom software compiles a circuit design's high- level description into a low level binary representation that can… more
- Cadence Design Systems, Inc. (Austin, TX)
- …3DIC. + Working with customers in one or more of the following areas: Synthesis , Place and Route, timing and power signoff. + Understanding and proliferating Cadence ... and compensation may vary based on factors such as qualifications, skill level , competencies and work location. Our benefits programs include: paid vacation and… more
- NVIDIA (Santa Clara, CA)
- …full chip designs or at block- level with additional responsibilities for block level synthesis /optimization + You will be responsible for all aspects of ... Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing...in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills… more
- Qualcomm (Austin, TX)
- …related to synthesis . hard macro integration, placement, clock tree synthesis (CTS), routing, and overall physical design convergence. deliverables include ... implementation flows for optimum PPA (power, performance, and area). + Perform synthesis placement and create handoffs to top- level chip teams. + Lead… more
- Siemens Digital Industries Software (Costa Mesa, CA)
- …potential customers to identify technology or operational challenges in their existing physical design flows, then use developing relationships and deep knowledge to ... have hands-on expertise in RTL to tape-out digital implementation, including synthesis , place-and-route, PPA closure, and related sign-off verification. This comes… more
- The Boeing Company (Tukwila, WA)
- …Summary pay range Lead Level 4: $126,650.00 - $171,350.00 Summary pay range Senior Level 5: $155,550.00 - $210,450.00 Applications for this position will be ... SiGe. SSED uses external wafer fabrication but performs design (architecture, RTL, synthesis , circuits, physical design, verification), packaging, and test in… more