We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- …this massive superchip. We are looking for expert engineers to come and help design Datacenter level power management solutions for next generation scaling AI ... of technologies. You will play a key role in power management software architecture, design and implementation;...system, algorithms and data structures. + In depth knowledge low level power management fundamentals like DVFS,… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Applied Power Architect - GPU. NVIDIA is known as a world leader in providing energy-efficient high-performance products, and we ... + MSEE/MSCE, preferably PhD, or equivalent experience with a specialization in low - power -processor architectures. + Strong knowledge of energy efficient system … more
- NVIDIA (Santa Clara, CA)
- …energy efficient chip/system design fundamentals and related tradeoffs. + Familiarity with low power design techniques such as multi-VT, Clock gating, ... We are looking for a Senior Datacenter GPU Power Architect. NVIDIA...improvements. + Pre-silicon thermal analysis for next-gen GPUs including design of thermal usecases, power map for… more
- NVIDIA (Santa Clara, CA)
- …(in design and process) and craft solutions to address those + Explore and implement low power design ideas by finding the right balance with timing and ... looking for a motivated Senior ASIC Physical Design PPA (Performance, Power , Area) Engineer to...physical design and timing of high-frequency and low - power designs + Focus on improving the… more
- NVIDIA (Santa Clara, CA)
- …metrics from each device + Strong knowledge of firmware architecture, optimize firmware for low latency APIs. Proven record of power optimization for large data ... HPC and generative AI workload.Scale out is inherent to design of this massive superchip. We are looking for...advancement. What you'll be doing: + Drive next generation power management solutions for scaling AI infrastructure using GPUs… more
- NVIDIA (Santa Clara, CA)
- …you will be responsible for the design and implementation of high-performance, low power CPU sub-system modules. You will work closely with architects, ... We are looking for a Senior CPU Design Engineer! NVIDIA is... skills to optimize and meet performance, timing and power targets. + Deliver a synthesis/timing clean design… more
- NVIDIA (Santa Clara, CA)
- …+ Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation. + Collaborate with ... We are now looking for a Senior Logic Design Engineer! Asa member...with implementation to achieve your timing, area, performance and power goals. + Assist with timing closure of super… more
- Capgemini (Santa Clara, CA)
- …authorization in Canada by Capgemini **Job description:** We are looking for Senior Design Verification Engineer **Key responsibilities:** + Proficient in System ... end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading...**Nice to have skills:** + GLS verification knowledge + Low power - UPF - verification +… more
- NVIDIA (Santa Clara, CA)
- …running Spice and experience with timing analysis/closure is required. + Hands on experience in design and analysis of low power circuits ( power gating, ... you'll be doing: + Participate in ground breaking Processor design in deep submicron technologies. + Work as part... innovative circuits for hardware security, adaptive clocking and power management solutions + Apply circuit techniques to improve… more
- NVIDIA (Santa Clara, CA)
- …you'll be doing: + Drive physical design and timing of high-frequency and low - power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level. ... We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic...including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. + Work in a… more
- NVIDIA (Santa Clara, CA)
- …analytical skills. + Prior working experience with display/video image processing blocks and design techniques for low - power . NVIDIA is widely considered to ... We are now looking for a Display ASIC Design Engineer! NVIDIA is seeking a passionate ASIC...the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear… more
- Capgemini (Santa Clara, CA)
- …Debug skills at IP and subsystem level Good to have: * GLS verification knowledge * Low power - UPF - verification * ARM based SoC level verification experience ... to transform and manage their business by harnessing the power of technology. The Group is guided every day...end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …definition, as well as RTL design to achieve high performance and low power . Familiarity with NoC technology and concepts, AMBA protocols (AXI, AHB, ... an impact on the world of technology. Successful applicant will participate in the design and development of a fully configurable and fully featured Network on Chip… more
- Microsoft Corporation (Sunnyvale, CA)
- …flows. + Highly proficient in Verilog/System Verilog. + Experience in high performance and low power design techniques. + Understanding of IP development & ... a variety of disciplines including, but not limited to, design , verification, performance modeling and DevOps supporting the development... quality checks such as Lint, CDC, RDC, and Low Power Intent analysis. + Coordinate closely… more
- Qualcomm (Santa Clara, CA)
- …of the entire chip . Design quality check such as lint, CDC and low power rule checks . RTL-level and gate-level vector-based power analysis **Minimum ... development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers...design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit… more
- Microsoft Corporation (Santa Clara, CA)
- … Design release packaging and qualification, RTL quality flows, static checks. + Low Power design . **Other Requirements** Ability to meet Microsoft, ... Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis, RTL Power Analysis, Physical .../Unified Power Format (UPF) linting flows like Power Artist/Jules, Verification Checks Low Power… more
- Microsoft Corporation (Mountain View, CA)
- …equivalence failures. + Perform cross-functional decision making across UPF (Unified Power Format)/ Low Power methodology/architecture, DFT methodology, ... DFT methodology and handling DFT constraints for Logical Equivalence + Timing Constraints/ Low Power Static verification flows to augment pure functional… more
- Siemens Digital Industries Software (Fremont, CA)
- …applications. Map the requirements into software understandable format from Siemens EDA customers on low - power chip design (Unified Power Format (UPF) and ... such as Placement, Clock Tree Synthesis, Optimization and Routing. Work on physical design activities for advanced technology nodes. Assess power domain based… more
- NVIDIA (Santa Clara, CA)
- …complexities. + Basic understanding of fundamental concepts of energy consumption, estimation, and low power design . + Desire to bring quantitative ... and Analysis Team, you will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and… more
- Qualcomm (Santa Clara, CA)
- … Power Optimization: Implementing power -saving techniques and strategies to meet low - power design goals. * Physical Verification: Conducting design ... schematic (LVS) checks, ERC and other miscellaneous checks to ensure the physical design meets manufacturing requirements. * Power Integrity: Ensuring that the… more