- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive timing ... equivalent experience + At least 6+ years of relevant work experience in timing methodology and/or silicon data analysis/correlation roles. + Deep understanding… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role ... in improving the netlist and timing quality of our designs and if you are...teams. + Work on project execution as well as methodology improvements. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. + Finding the right tradeoffs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPUs, GPUs, SoCs at...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. What you'll be doing: + Drive DFT/Test timing for innovative GPUs, CPUs, and SoCs at cluster level and/or full chip ... level + Work on all aspects of DFT/Test timing such as timing constraints, timing...and clock controls in DFT modes + Experience in methodology or flow development + Great problem-solving skills, self-motivated… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... + Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Strong understanding of physical design implementation… more
- NVIDIA (Santa Clara, CA)
- …for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across ... + Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Familiar with various process related design… more
- NVIDIA (Santa Clara, CA)
- …looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus on improving the PPA… more
- Microsoft Corporation (Mountain View, CA)
- …sites within the Microsoft silicon engineering organization. We are looking for a ** Senior Silicon Engineer ** to join our team! **Microsoft's mission is to ... UPF (Unified Power Format)/Low Power methodology /architecture, DFT methodology , Synthesis, Place and Route and Extracted Timing... methodology , Synthesis, Place and Route and Extracted Timing model generation in Timing Analysis tools… more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We ... patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through...for high coverage on silicon - Review sign-off level timing closure using static timing analysis of… more
- BAE Systems (San Jose, CA)
- …be a part of? Come build your career with BAE Systems. We are seeking a very senior level engineer to: + Design and RTL coding of high-speed digital circuits on ... Other incentives may be available based on position level and/or job specifics. ** Senior Principal ASIC Design Engineer (Hybrid)** **95186BR** EEO Career Site… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... in one or more of the following areas: Synthesis, Place and Route, timing and power signoff. + Understanding and proliferating Cadence flow solutions in the… more
- SpaceX (Sunnyvale, CA)
- …of coding through LINT and clock domain crossing flows + Deploy and enhance methodology and flows related to timing constraint generation and verification and ... as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base… more
- Microsoft Corporation (Santa Clara, CA)
- The Microsoft Silicon Engineering and Solutions Team is looking to hire a ** Senior Silicon Engineer ** to join our Central Front-End Tools, Flows and ... Methodology (TFM **)** group. This team drives state-of-the-art converged...verify reusable design components. + Experience in Synthesis and Timing Constraints. Exposure to tools T, Fishtail, Formality/ Logic… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... ead. + Experience of succeeding in a highly matrix organization. + Driven process/ methodology improvements. The base salary range is 164,000 USD - 258,750 USD. Your… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- NVIDIA (Santa Clara, CA)
- …knowledgeable in DFT, digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... Lead. + Experience of succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is widely considered to be the leader of AI… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the development and implementation of products ... (like Cadence or Synopsys), semiconductor processes, and an understanding of timing closure, clock tree synthesis, power optimization, and physical verification… more