• SOC/ASIC Synthesis & Front-End STA

    SpaceX (Sunnyvale, CA)
    SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... with the ultimate goal of enabling human life on Mars. SOC/ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (05/09/24)
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  • Synthesis / STA Engineer

    Qualcomm (Santa Clara, CA)
    …help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems. Qualcomm ... for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state of the art Physical Synthesis Tools; Timing… more
    Qualcomm (04/18/24)
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  • Sr. SOC Design Engineer - STA

    Amazon (Sunnyvale, CA)
    …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. -… more
    Amazon (02/20/24)
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  • STA Engineer

    Arrow Electronics (San Jose, CA)
    **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power Analysis and… more
    Arrow Electronics (03/29/24)
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  • Physical Design Methodology Engineer

    Microsoft Corporation (Santa Clara, CA)
    …or related field. + 7+ years of physical design experience, including hands-on experience in synthesis , place & route, and STA . + 4+ years of experience with ... We are looking for a **Physical Design Methodology Engineer ** . As part of our DPU silicon...Qualifications:** + 10+ years of physical design experience (including synthesis , place & route, LEC, STA , physical… more
    Microsoft Corporation (04/26/24)
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  • Senior Physical Design and Timing Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... frontend and backend implementation from RTL to gds2, including synthesis , equivalence checking, floor-planning, timing constraints, timing and power convergence,… more
    NVIDIA (03/07/24)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... generation of CPU, GPU or SOC designs. + Owning STA of large subsystems and full chip designs or...or at block-level with additional responsibilities for block level synthesis /optimization + You will be responsible for all aspects… more
    NVIDIA (04/16/24)
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  • Senior ASIC Physical Design PPA Engineer

    NVIDIA (Santa Clara, CA)
    …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... with 6+ years experience in Physical Design + Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to achieve better… more
    NVIDIA (03/07/24)
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  • Application Engineer Architect- Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Digital Design Implementation & Signoff including Synthesis , Place and Route, Design Closure, and timing/power signoff + Guide customers ... (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with...tools in the IC digital implementation & signoff flows ( STA tools) + Strong STA and SDC… more
    Cadence Design Systems, Inc. (03/22/24)
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  • Principal Silicon Validation Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …gate level simulations to verify functionality. + Perform and help debug Synthesis / STA scripts/constraints. + Participate in development of Application notes, ... IP. + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end experience is a plus + Familiarity with industry… more
    Cadence Design Systems, Inc. (03/01/24)
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  • Senior CAD Flow Development Engineer

    NVIDIA (Santa Clara, CA)
    …is our life's work, to amplify human inventiveness and intelligence. Are you a software engineer with a passion for hardware, ASIC design and VLSI? Be part of a ... methodology! We're responsible for NVIDIA's front-end ASIC software including RTL synthesis , equivalence checking, and early physical design and methodology for all… more
    NVIDIA (05/07/24)
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  • Senior System On Chip Integration Engineer

    Microsoft Corporation (Sunnyvale, CA)
    …tools (Verilog simulators, Connectivity tools, CDC checkers, low power intent, linting, Synthesis , STA ). + Experience in designing for testability, debug, and ... passionate, driven, and intellectually curious **Senior System On Chip Integration Engineer ** to deliver premium-quality designs once considered impossible. Our team… more
    Microsoft Corporation (05/09/24)
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  • SoC Integration Engineer - Onsite

    ManpowerGroup (San Jose, CA)
    …innovate in an unparalleled time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can help along the design flow to ... establish synthesis runs with the related timing constraints, perform Lint,...DFT checks, support regression and release process and analyze STA timing results. **Here's what you need:** + A… more
    ManpowerGroup (03/22/24)
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  • SoC Physical Design Engineer

    Google (Sunnyvale, CA)
    …route, or physical verification. + Experience in physical design areas such as synthesis , place and route, STA , formal verification, or power analysis. Preferred ... software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the world's… more
    Google (05/11/24)
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  • Senior ASIC Engineer , Timing

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... including clock domain crossing checks and MTBF analysis, logic synthesis , netlist quality checks, etc. + Help in all...timing issues, timing constraints and clocking. + Expertise in STA tools and methodologies for timing closure with a… more
    NVIDIA (04/18/24)
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  • NoC Interconnect Design Engineer

    Qualcomm (Santa Clara, CA)
    …tradeoff analysis and performance trouble shooting. + Strong knowledge of ASIC flow ( synthesis , STA , Lint), power tools. + Ability to define bus components ... power interconnect. Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with… more
    Qualcomm (04/10/24)
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  • Lead Digital Implementation Applications…

    Cadence Design Systems, Inc. (San Jose, CA)
    …+ Working with customers in one or more of the following areas: synthesis , Place and route, signoff + Understanding and proliferating Cadence flow solutions in ... EDA tools is required, ie; Genus, Design Compiler, Innovus, ICC2, Conformal, Tempus, STA , Static Timing Analysis, PrimeTime, Modus, and/or Voltus is highly desired +… more
    Cadence Design Systems, Inc. (05/10/24)
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  • Sr. Digital Design Engineer

    Integense (San Jose, CA)
    …mass production. + Experienced in all Front and Back End activities - RTL, Verification, Synthesis , STA , DFT, ATPG, etc. + Adept with System Verilog, C, and ... various scripting languages. + Experience with, implementing, designing with, and testing standard interfaces (I2C/SPI/APB/AHB). + Excellent English written and verbal communication skills. Preferred Qualifications + Experience implementing embedded… more
    Integense (03/27/24)
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  • Sr. ASIC Design Engineer , Blink/Ring ASIC…

    Amazon (Sunnyvale, CA)
    …front-end tools including: Synthesis , Lint (RTL, DFT, UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage ... -Work with pre-silicon verification teams to assist in defining testplans/testbenches -Work with post-silicon validation teams to define and execute on testplans -Write high quality documents to guide and lead a scalable team We are open to hiring candidates… more
    Amazon (03/27/24)
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