- Cisco (Portland, OR)
- ASIC DFT Product Lead Apply (https://jobs.cisco.com/jobs/Login?projectId=1435540) + Location:Portland, Oregon, US + Alternate LocationPortland, OR, USA + Area of ... **Your Impact** : You will be in the Silicon One development organization as an ASIC DFT Product Lead in San Jose, CA with a primary focus on Design-for-Test and… more
- Northrop Grumman (Morrisville, NC)
- …making history. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse ... DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for DFT (Design for Testabilty) aspects of ASIC ...for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts +… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT Responsibilities: 1. Develop and implement DFT strategies for data… more
- Amazon (Austin, TX)
- …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
- Qualcomm (Santa Clara, CA)
- …in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 2+ years of practical experience with test ... create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip...designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and… more
- NVIDIA (Santa Clara, CA)
- …yield enhancement and spec validation + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... teams to coordinate efforts and resolve silicon issues + Initiate and drive process improvements/preventative actions through root cause analysis + The ideal candidate will always look to improve workflows, products, functions and methodologies while working… more
- Cadence Design Systems, Inc. (Cary, NC)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate ... testbenches. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the… more
- Cisco (San Jose, CA)
- ASIC Engineering Technical Leader - SDC Apply (https://jobs.cisco.com/jobs/Login?projectId=1434557) + Location:San Jose, California, US + Area of InterestEngineer - ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
- Qualcomm (San Diego, CA)
- …premium Snapdragon chip sets and is seeking Hardware Design engineers with solid ASIC design experience in San Diego, CA. This is a high-level, high-profile ... degree in electrical engineering, or related Sciences + 6+ years of experience in ASIC design + Experience and understanding of ASIC design flow: Architecture,… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical...with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- RTX Corporation (Cedar Rapids, IA)
- …clearance **Security Clearance:** DoD Clearance: Secret **Senior Electrical Engineer** **- ASIC /FPGA (Onsite)** This position is for a motivated Senior Electrical or ... Product Enabling Technologies team. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure,… more
- Cisco (San Jose, CA)
- ASIC Engineering Technical Leader (Design) Apply (https://jobs.cisco.com/jobs/Login?projectId=1437840) + Location:San Jose, California, US + Area of InterestEngineer ... working together to ensure the successful deployment of the ASIC in products. **Your Impact** + Development of high-performance...our design methodology. + Collaborate with the verification, PD, DFT , Package and SW teams to develop next generation… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367) + Location:San Jose, California, US + Area of ... systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing...Full chip Flat & Hierarchical Constraints for Functional & DFT Modes 3. Perform STA for full chip and… more
- Broadcom (San Jose, CA)
- …challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... of experience developing, implementing, and testing high performance communications/networking ASIC products. Experience in mapping communications algorithms or standards… more