- eTeam, Inc. (Chicago, IL)
- … design , digital microarchitecture, and SoC integration. Experience with design -for-verification methodologies and IP integration. <,> Preferred Skills 10+ ... Job Title: Silicon DD Engineer IV Location: Onsite - Redmond, WA (Sunnyvale,...development team. The ideal candidate will contribute to the design , development, and validation of RTL modules for FPGA… more
- Meta (Sunnyvale, CA)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Menlo Park, CA)
- …a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/ IP /System on Chip ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Sunnyvale, CA)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Sunnyvale, CA)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Sunnyvale, CA)
- …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Evaluate, develop and ... and NOC subsystems 15. 4. SystemVerilog/UVM methodology or C/C++ based verification 16. 5. ASIC development cycles 17. 6. IP /sub-system or SoC (System On Chip)… more
- Meta (Sunnyvale, CA)
- …on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/ IP /SoC verification plans, ... functional tests based on verification test plan. 3. Drive Design Verification to closure based on defined verification metrics...verification. 8. 2. Track record of 'first-pass success' in ASIC development cycles. 9. 3. Experience in block/ IP… more
- Meta (Austin, TX)
- …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...2. Micro-architecture development 3. Soft and hard IP identification, selection and integration. Collaboration with verification and… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Verilog, System Verilog and HLS 4. Soft and hard IP identification, selection and integration 5. Collaboration with verification… more
- Meta (Jackson, MS)
- …on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, build ... IP /SoC (System On Chip) Verification 10. 4. Debugging design 11. 5. Functional Coverage 12. 6. Automation Scripting...to $287,650/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design &...multiple timing modes + Option to also do block level RTL design or block or top-level IP integration + Helping ... systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record...of what's possible! **Your Impact** You are a diligent Design /SDC Engineer with strong analytical skills and… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... 4. Deliver physical design of an end-to-end IP or integration of ASIC /SoC design...to $291,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an… more
- Amazon (Austin, TX)
- … design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze...innovate, explore new solutions, and contribute to the company's intellectual property through patents About the team… more
- Arrow Electronics (San Jose, CA)
- **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs onto ... prototyping methodology. + **Option to engage in block-level RTL design or block or top-level IP integration.**...by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree… more
- NVIDIA (Austin, TX)
- …can make a lasting impact on the world. Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on ... improving methodologies and delivering system-level IP to measure performance across multiple projects. What you'll...system + Run and debug RTL checks to ensure design quality (eg, cross clock domains (CDC), clocks, reset,… more
- Amazon (Sunnyvale, CA)
- …around the world. Come work at Amazon! We're hiring a Sr. Modem Design Engineer within a high performance ASIC design team. This team is using ... industry leading methodologies to develop proprietary IP 's. The Role: Be part of Project Kuiper's sub-team...models in MATLAB. - Involve in control plane logic design and interfaces to bus fabrics. - Explore and… more
- Amazon (Austin, TX)
- …. Define and develop any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on ... refugee or granted asylum. Key job responsibilities Key job responsibilities RTL Design and development of custom blocks. Integration of large subsystems Gate Level… more
- Amazon (Austin, TX)
- …. Define and develop any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on ... Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic… more
- NVIDIA (Santa Clara, CA)
- NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. ... This role requires working with multiple teams as Architecture, IP , Physical design , Timing and Post-Si teams....design next generation clock topologies and modules. + ASIC Clock scheme definition. + Improve Power, Performance, and… more
- Amazon (Sunnyvale, CA)
- …specifications suitable for being implemented by junior engineers -Evaluate 3rd party IP blocks -Estimate power, performance, and area for significant IPs early in ... design cycle -Execute on design specifications to deliver high quality RTL -Ensure quality by running and tracking results of front-end tools including:… more
