- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our customers. We are ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs.… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- L3Harris (Camden, NJ)
- …land, sea and cyber domains in the interest of national security. Job Title: ASIC /FPGA Design Engineer (SMES) Job Code: 26283 Job Location: Camden, NJ Schedule: ... in the amount of $ 15,000 . Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... in Physical design/Timing. + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Cisco (San Jose, CA)
- ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US + ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/DFT/LEC/ STA ) + Partner and work with back-end team until chip tape-out. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... with 2 years' experience + Experience with Static Timing Analysis ( STA ) + Experience physical design and optimization eg, synthesis, floorplanning, placement,… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more
- Cisco (Maynard, MA)
- Senior ASIC Timing Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1449290) + Location:Maynard, Massachusetts, US + Area of InterestEngineer - ... in a highly team focused environment. + Involves in static timing analysis ( STA ) methodology and flow. Including but not limited to latest timing technologies, like… more
- NVIDIA (Santa Clara, CA)
- …years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs. + Strong background ... and experience in timing constraints generation, clocking, process variations and signal integrity + Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies. +… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Broadcom (Irvine, CA)
- …and 12+ years of industry experience in flow development , synthesis constraints development / STA is a must, or MSEE and 10+ years of industry experience. A strong ... be responsible for working on automating design flows, supporting synthesis deliverables & STA . Apart from this, the candidate is also expected to handle minimal… more
- Amazon (Sunnyvale, CA)
- …of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage ... -Work with pre-silicon verification teams to assist in defining testplans/testbenches -Work with post-silicon validation teams to define and execute on testplans -Write high quality documents to guide and lead a scalable team Basic Qualifications -Bachelor's… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for ... phases of SoC DFT related activities for Broadcom APD ( ASIC Products Division)'s designs - DFT Architecture, Test insertion...metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role… more
- NVIDIA (Santa Clara, CA)
- …Are you a computer engineer with a passion for automation of VLSI ASIC design? Be part of a diverse team creating NVIDIA's chip design methodology! These chips ... and use advanced silicon processes. We're responsible for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design… more
- Broadcom (Fort Collins, CO)
- …the physical design team to aid in overall closure and manufacture of the ASIC with emphasis on low power, optimized area, max. performance and high overall ... candidate should have a strong understanding of VLSI and ASIC physical design 12+ years of experience w/ a...to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC networks and… more