- Broadcom (Fort Collins, CO)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** **IP STA Champion Description** **Main Goals** **1. Work with DA STA Team ... quality ETM or Liberty timing models that meets APD STA standards:** + **Correct timing modes that align with... background** + **Should be familiar with APD DI design flows** + **Bachelors and 12+ years of related… more
- Cadence Design Systems, Inc. (Austin, TX)
- …the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to ... and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to… more
- Cadence Design Systems, Inc. (Austin, TX)
- …the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to ... on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various… more
- Broadcom (Irvine, CA)
- …strong team player. Candidates will primarily be responsible for working on automating design flows, supporting synthesis deliverables & STA . Apart from this, ... of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products....experience in flow development , synthesis constraints development / STA is a must, or MSEE and 10+ years… more
- Arrow Electronics (San Jose, CA)
- **Position:** Physical Design Engineer (Einfochips Inc) **Job Description:** **What candidate will Be Doing:** + Netlist to-GDSII implementation, including ... top-level floorplanning,, Design partitioning, Top level block to block/over the block...simulation, power mesh planning, and full signoff (DRC, LVS, STA , EMIR). + Own and drive PnR execution and… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and reliability through increasingly comprehensive modeling, informative analysis, and automation . This work will influence the entire next generation computing… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various… more
- Meta (Sunnyvale, CA)
- …stack, from transistor, through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you will perform physical ... area requirements needed for our wearable products. **Required Skills:** SoC Physical Design Engineer Responsibilities: 1. Physical design implementation… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring ... of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various… more
- NVIDIA (Westford, MA)
- …inventiveness and intelligence. NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer who is dedicated to collaborating closely with ... optimize for area, power, and timing. + Run physical design flow from netlist to GDS, perform STA...netlist checks and formal equivalence validation. + Enhance tool automation , streamline workflows, and document best practices. What we… more
- Amazon (Austin, TX)
- …member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide leadership ... possible today. Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test (DFT) architectures * Work with block designers to… more
- NVIDIA (Santa Clara, CA)
- …cross-domain timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're ... Python) for automation and flow development. + Experience working with STA tools like Synopsys PrimeTime or Cadence Tempus. + Deep understanding of clocking… more
- NVIDIA (Santa Clara, CA)
- …lasting impact on the world. Are you a computer engineer with a passion for automation of VLSI ASIC design ? Be part of a diverse team creating NVIDIA's chip ... design methodology! These chips are among the largest and...ASIC methodologies such as RTL Lint, CDC, DFT or STA . + Familiarity with Machine Learning/Deep Learning NVIDIA is… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to ... on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job...-for-Test (DFT), Place & Route and Static Timing Analysis ( STA ).You may get involved in design services… more
- Meta (Sunnyvale, CA)
- …12. Develop automation scripts and methodology for FE-tools. 13. Support design engineers, DV engineers, and emulation engineers with handoff tasks. 14. Give ... to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Engineer in Custom Timing to join our dynamic and growing team. If you are looking for a challenging and exciting ... you'll be doing: + Participate in cutting edge Processor design in deep submicron technologies. + Work as part...+ Expertise and in depth knowledge of industry standard STA tools such as NanoTime and PrimeTime. + Experience… more
- Broadcom (Mendota Heights, MN)
- …before you apply.** **Job Description:** We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of ... + Place and route expertise + Proficient in running STA , DRC, EM/IR tools, and attaining design ...+ Familiar with memory behavior + Proficient in writing automation scripts, and tools savvy + Good communication, interpersonal,… more
- Cisco (San Jose, CA)
- …it from concept to first customer shipments **Your Impact** You are a diligent Design /SDC Engineer with strong analytical skills and a deep understanding of ... ASIC Design Technical Leader - Design &...clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation , you… more
- NVIDIA (Westford, MA)
- …and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing ... a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level,… more