- Nvidia Corporation (Santa Clara, CA)
- …member of the DFX methodology team, you will be responsible for the architecture, design , implementation and verification of fuse controller and other DFT IPs ... designs using vendor tools Good exposure to cross functional areas including RTL & clocks design , STA , place-n-route and power, to ensure we are making the right… more
- Qualcomm (Santa Clara, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Microsoft Corporation (Hillsboro, OR)
- …semiconductor designs. + Collaborate with design , implementation , and physical design teams to define and drive timing constraints and methodology. + ... the Cloud infrastructure. We are looking for a **Principal Timing / STA Engineer** to join the team. **Responsibilities**...targets. + Work closely with cross-functional teams to resolve timing issues, optimize design performance, and meet… more
- Amazon (Portland, OR)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf of our customers. We are ... Includes definition and development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk...& Route and other local/remote teams to address the design challenges in the context of timing … more
- Qualcomm (San Diego, CA)
- …+ Experience in static timing analysis, constraints and other physical implementation aspects + Familiar with digital flow design and industry standard ... tools used for RTL to GDS implementation + Good technical writing and communication skills in...debug across multi-mode, multi-voltage domain designs using industry standard timing tools + STA setup, convergence, reviews… more
- Qualcomm (San Diego, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Meta (Austin, TX)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... scripts and Methodology for all FE-tools including ( Synthesis, STA ) 6. Work closely with the Design ...supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing /congestion… more
- NVIDIA (Santa Clara, CA)
- …and/or full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, ... timing and power convergence, and ECO implementation . + Work in a cross-functional environment interacting with... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
- NVIDIA (Santa Clara, CA)
- …in Physical design / Timing . + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and ... as timing constraints, timing analysis, timing convergence, and ECO implementation . What we...multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg cell… more
- Google (Sunnyvale, CA)
- …about benefits at Google (https://careers.google.com/benefits/) . + Debug and resolve common Static Timing Analysis ( STA ) or design rule issues like ... + Experience writing, reviewing and verifying complex TCL constraints for static timing analysis. + Experience in extraction of design parameters, QoR… more
- NVIDIA (Santa Clara, CA)
- …or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation , and ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and...to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power...including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation .… more
- Capgemini (CO)
- … at both block and full-chip levels. + Solid experience with multi-voltage design implementation ; experience in STA closure for low-power and ... the Job You're Considering** + Develop block-level and SoC-level timing constraints, and drive full-chip STA setup...flows and analysis tasks. + Hands-on experience with physical design implementation is a plus. + Excellent… more
- Meta (Austin, TX)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power) 9. Work closely with the Design...supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Microsoft Corporation (Austin, TX)
- … (PD) domain. + Facilitate coordination across cross-functional teams, including DFT, RTL/ Design /IP, Static Timing Analysis ( STA ), CAD, Architecture, Power ... SoC/CPU designs. + Expertise in Engineering Change Order (ECO) implementation for power/ timing convergence. Solid grasp of...STA , driving timing optimization, and achieving timing closure. + Thorough understanding of design … more
- Broadcom (Fort Collins, CO)
- …error messages from the timing tool - Ability to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC ... analysis, and other timing checks - Ability to understand and create timing diagrams Deep understanding of more advanced STA concepts - POCV/SOCV/LVF… more
- Qualcomm (San Diego, CA)
- …for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have good ... **Experience in leading block level or chip level Physical Design , STA and PDN activities** . +...Work independently in the areas of RTL to GDSII implementation . + Ability to collaborate and resolve issues wrt… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best ... related experience in design and EDA (Digital Implementation /Signoff) + Understands ASIC Design implementation...+ Experience with EDA tools in the IC digital implementation & signoff flows ( STA tools) +… more
- SanDisk (Milpitas, CA)
- …teams and back-end implementation engineers to perform physical verification, static timing analysis ( STA ), and tape-out readiness. You will apply deep ... in advanced 3D NAND Flash memory, with a focus on microarchitecture, RTL design , verification, logic synthesis, and static timing analysis. The goal is to… more
- Meta (Sunnyvale, CA)
- …levels. From microarchitecture definition and RTL implementation to synthesis and timing closure, fundamentals in digital design will enable you to ... collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4. Drive IP/sub-system micro-architecture and RTL … more
