- NVIDIA (Santa Clara, CA)
- …make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly ... to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art GPUs to power AI,… more
- Meta (Sunnyvale, CA)
- …technology. To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Develop power vectors ... for estimation and optimization. 2. Low - power design of ASIC modules. 3. Run industry standard EDA power simulation tools on customized ASIC designs.… more
- Google (Sunnyvale, CA)
- Senior ASIC Power Engineer , ML...Level) design using Verilog or SystemVerilog. + Experience with low - power design or power reduction ... + 5 years of experience in logic design, digital ASIC , or SoC design. + Experience with RTL (Register...techniques. + Define best practices and methodologies to achieve low - power RTL designs. + Collaborate with cross-functional… more
- SpaceX (Irvine, CA)
- …AHB, etc.) + Experience with embedded processors + Experience with high speed and low power design techniques + Scripting skills (Python, TCL etc.) + Experience ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...to solve complex problems including clock domain crossings and power optimization + ASIC /SoC system integration experience… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning 19. Experience with low power implementation, power gating,… more
- Teledyne (Goleta, CA)
- …analysis. + DFT/ATPG insertion (scan chains, BIST for ASIC testability). + Clock/ Power optimization for low - power ASICs. + Perform Back-End Physical ... on a team that wins. **Job Description** **Job Summary:** ASIC Digital Design Engineer : Oversees definition, design,...windowing). + Finite State Machine and datapath design for ASIC modes. + Clock domain crossing and power… more
- ManpowerGroup (Phoenix, AZ)
- **Job Title: Physical Verification Engineer ( ASIC Design)** **Location: USA & Canada (Remote is OK, Phoenix or Ottawa preferred)** **Role Overview** As a ... **Physical Verification Engineer ** , you...(Nice to Have)** + Experience with **multi-voltage designs** and ** low - power verification** (UPF/CPF). + Familiarity with **DFM… more
- Meta (Harrisburg, PA)
- …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 22. Experience with development of… more
- The MITRE Corporation (Bedford, MA)
- …high throughput signal processing algorithms + Tightly integrated, custom platforms targeting low size, weight, power and cost (SWaP-C) applications + ... in Field-Programmable Gate Array (FPGA) and/or Application-Specific Integrated Circuit ( ASIC ) design to support advanced research and development projects of… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...for testability (eg, IEEE 1500, 1687) and experience with low - power DFT techniques using Siemens Tessent +… more
- Amazon (Austin, TX)
- …design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area ... Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses… more
- Google (Mountain View, CA)
- Senior ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and ... years of industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies… more
- Amazon (Austin, TX)
- …any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform ... Description Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low -latency, high-speed broadband connectivity… more
- Sandia National Laboratories (Albuquerque, NM)
- …regulators. + Expertise in the requirements and design of radiation-hardened circuits, low - power systems, or deployed sensors. + Solid understanding of device ... and Designs, is looking for an early-career Analog Mixed Signal IC Design Electronics Engineer to join our team focused on developing advanced CMOS chips. The chosen… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... What you'll be doing: + You will drive physical design of high-frequency and low - power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level,… more
- NVIDIA (Westford, MA)
- …will be doing: + You will drive physical design and timing of high-frequency and low - power DPUs and SoCs at block level, cluster level, and/or full chip level. ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering… more
- Amazon (San Diego, CA)
- …- Experience with products that have gone to volume production - Experience in low power design techniques Preferred Qualifications - Master's degree or Ph.D. ... Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing… more
- Amazon (Sunnyvale, CA)
- …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities -Define architecture specifications based on requirements… more
- Amazon (North Reading, MA)
- …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Use and/or build bit accurate C models - Evaluate block… more