- NY CREATES (Albany, NY)
- …innovation and commercialization. Job Description: Job Description for Photonics Integration Engineer This posting is to hire an experienced Process Integration ... Engineer working on our Silicon Photonics technology platforms. This...include, but are not limited to: Handling 3rd party design IP. Design rule checking and waiver… more
- Aquent (Cupertino, CA)
- …the circuit design team. Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area ... 3 years of experience with each of the following skills is required: Layout design of tight matching, low noise, and low power analog blocks, resistors,… more
- HyperLight (Cambridge, MA)
- …to automate layout procedures such as design -rule checking (DRC), layout -versus-schematic (LVS), and mask preparation. As a Photonics Layout ... care for one another. We are seeking a Photonics Layout Automation Engineer to join our growing...device component selection. Develop tool chains for automation of layout processes like LVS, DRC, and mask … more
- Jamie Grayem (Santa Clara, CA)
- Sr Analog IC Design Engineer Santa Clara, CA / Hybrid Remote140-200K + Signing Bonus + Paid Relocation CE AMS ACE PHY group supports analog mixed signal product ... link budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask design for implementation.… more
- Texas Instruments (Dallas, TX)
- …28nm, and 20nm processing nodes; FEOL integration a plus Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout ... Job Description Change the world. Love your job. A Process Development Engineer is responsible for the development, characterization and optimization of MEMS… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... Northrop Grumman Mission Systems is seeking a Semiconductor Equipment Engineer Level 3 / 4 for our Advanced Technology...- located outside of Baltimore, Maryland - where we design , manufacture, and test semiconductor products for internal and… more
- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask ... Have a BSEE or equivalent experience with Minimum of 5+ proven experience in Mask and Layout Design . + Deep understanding of analog circuit layout … more
- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a ... a BSEE or equivalent experience. + Minimum of 7+ years industry experience in Mask and Layout Design . + Deep understanding of analog circuit layout … more
- MIT Lincoln Laboratory (Lexington, MA)
- …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... radiation-hard CMOS, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which...in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Mask Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... hardworking, creative, and highly motivated engineers to work on the physical layout design and development of our next generation custom SRAM macro-IPs. As part… more
- Capgemini (Minneapolis, MN)
- …find the fastest way to complete layout * Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent ... **About the job you're considering** * 10 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent… more
- MIT Lincoln Laboratory (Lexington, MA)
- …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... engineer will collaborate with others involved in mask layout from basic layout ...o Programming in Perl, TCL, or Python o RF layout design experience o Experience with Cadence… more
- Texas Instruments (Dallas, TX)
- …28nm, and 20nm processing nodes; FEOL integration a plus + Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout ... **Change the world. Love your job.** A Process Development Engineer is responsible for the development, characterization and optimization of MEMS resonator devices… more
- IBM (Yorktown Heights, NY)
- …hardware testsites * Connectivity/schematic capture for quantum hardware releases * Detailed mask layout and chip finishing for quantum hardware releases * ... experience (Ansys Electronics Desktop, Keysight Momentum, Cadence Clarity etc.) * Mask /PCB layout experience (Cadence Virtuoso, KLayout, Synopsys Custom… more
- Global Foundries (Malta, NY)
- …www.gf.com . Summary of Role: GlobalFoundries Fab8 is seeking a motivated R&D design enablement engineer to become part of our state-of-the-art 300mm fabrication ... design rules , library device ( TSV) layouts, layout vs schematic( LVS) requirements , device model terminals....vehicle content specifications and the associated tapeout process (including mask reviews ). + Develop expertise in drafting test… more
- Texas Instruments (Dallas, TX)
- …role requires a strong understanding of lithography, RET (Resolution Enhancement Technology), layout design , and process integration. You will collaborate with ... environment. + Excellent problem-solving, analytical, and communication skills. + Familiarity with layout design tools (eg, Cadence Virtuoso). + Knowledge of … more
- Northrop Grumman (Manhattan Beach, CA)
- …the Northrop Grumman Microelectronics Center. Candidate will be primarily responsible for lithography mask layout using computer aided design (CAD) with ... Grumman Mission Systems has an opening for a Microelectronics Layout Engineer to join our team of...location in Redondo Beach, CA. SPF is where we design , manufacture, and test semiconductor products for internal and… more
- Micron Technology, Inc. (Richardson, TX)
- …flows, and methodologies for next-generation memory designs. Collaborating closely with design , layout , verification, modeling, and process teams, you will ... to provide an outstanding opportunity for a Staff CAD Engineer to join our Engineering Automation (EA) organization at...HBM, and Emerging memory designs. + Collaborate closely with design , layout , verification, modeling, and process teams… more
- Skyworks (Irvine, CA)
- Staff Electrical Engineer Apply now " Date:Jul 26, 2025 Location:...for RF front end modules which is including CAD layout and photo mask tapeout process as ... are changing the way the world communicates. Requisition ID: 75506 BAW filter NPI engineer This Acoustics NPI engineer position will be working as a core… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... your career today. Northrop Grumman Mission Systems is seeking a **Semiconductor Equipment Engineer Level 3 / 4** for our Advanced Technology Lab (ATL) - located… more
