- Palo Alto Networks (Santa Clara, CA)
- …and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi- chip -module designs + Model and analyze power delivery networks ... in-person interactions. This is why our employees generally work full time from our office with flexibility offered where...the Hardware team, you collaborate closely with Board Design, ASIC Design, PCB Layout, and Validation Test. You will… more
- Cisco (San Jose, CA)
- Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San Jose, California, US + Area of InterestEngineer - Hardware ... Verilog RTL to meet timing, performance, and power requirements. + Contribute to full chip integration and timing methodology/analysis. + Develop and analyze… more
- Draper (Boston, MA)
- Job Description Summary: We are seeking a Senior Analog/Mixed Signal ASIC Design Engineer to join our team in the Silicon Architecture group. Members of our ... most efficient design solution. We are involved in the full design lifecycle and often take chip -lead...or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related. Additional Job Description: Additional… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to… more
- NVIDIA (Santa Clara, CA)
- …of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Synthesis and Timing + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA),… more
- NVIDIA (Santa Clara, CA)
- …and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Work with PD, DFX, Clocks, and other teams in coming ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Timing and STA + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA)… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... experience. + 8+ years experience in Physical design/Timing. + Experience in full - chip /sub- chip Static Timing Analysis (STA), timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... Create and execute test plans to support both functional and DFT full - chip verification. + Support post-silicon bring-up and validation efforts including debug… more
- Tarana Wireless (Milpitas, CA)
- …that you will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate ... to define verification strategies and execute plans at system or full chip level + Build and continuously improve verification infrastructure and methodologies… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic ... of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.… more
- Amazon (Cupertino, CA)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more
- Amazon (San Diego, CA)
- …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power...of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For… more
- Amazon (San Diego, CA)
- …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... to facilitate testing of RTL at both block and chip -levels * Incorporate reference Matlab/C models in verification environments...of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For… more
- Amazon (Austin, TX)
- …low-latency, high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA ... the versions of the tools, flows, design IPs, other collateral for every chip in development. Additionally, you will interface various digital design teams who will… more
- Capgemini (CO)
- …You're Considering** + Develop block-level and SoC-level timing constraints, and drive full - chip STA setup and signoff for multi-corner, multi-voltage designs. + ... + Develop block and SoC timing constraints, and perform full - chip STA setup and signoff for multi-corner,...and Experience** + 10 years of professional experience in ASIC implementation and CAD methodology, with a strong preference… more
- Google (Sunnyvale, CA)
- …experience. + 5 years of experience in static timing analysis. + Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off ... endpoints, maximum transition, minimum period, or minimum pulse width violations. + Perform full chip static timing analysis, timing ECO creation for timing… more
- Cisco (San Jose, CA)
- …IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. ... Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose,...be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with… more
- Huntington Ingalls Industries (Fort Meade, MD)
- Requisition Number: 23335 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Anticipated Salary Range: $116,245.00 - $165,000.00 Security Clearance: ... TS/SCI with Poly Level of Experience: Senior This opportunity resides with Warfare Systems (WS), a...and vulnerabilities in the gate-level netlists of FPGA and ASIC designs. Candidates for this position will help lead… more
- quadric.io, Inc (Burlingame, CA)
- …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of ... Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + BS/MS or Ph.D.… more
- Huntington Ingalls Industries (Roanoke, VA)
- Requisition Number: 23851 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Anticipated Salary Range: - $135,000.00 Security Clearance: Ability to ... Obtain Level of Experience: Senior This opportunity resides with Warfare Systems (WS), a...and vulnerabilities in the gate-level netlists of FPGA and ASIC designs. Candidates for this position will help lead… more