- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... Be Doing: + Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Work with front-end teams to overlook correctness of the design (Lint/NA/ CDC /Synthesis/DFT/LEC/ STA ) + Partner and work with back-end team until chip… more
- Renesas (Duluth, GA)
- Senior Staff Digital Engineer Job Description + **Education:** Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or ... and route constraints + Proficiency in formal verification, linting, and CDC /RDC checking + Knowledge of asynchronous clock crossings and synthesis implications… more
- NVIDIA (Santa Clara, CA)
- …Machine Learning/Deep Learning + Experience in other ASIC methodologies such as RTL Lint, CDC , DFT or STA . + Experience with compute farm interaction: software ... deployment, performance optimization, containers, etc. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working… more
- L3Harris (Camden, NJ)
- …cyber domains in the interest of national security. Job Title: ASIC/FPGA Design Engineer (SMES) Job Code: 26283 Job Location: Camden, NJ Schedule: 9/80 Regular with ... of $ 15,000 . Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA… more