- Northrop Grumman (Linthicum Heights, MD)
- …and Static Timing Analysis would be a plus + Active Clearance or higher ** Senior Principal Engineer Basic Qualifications:** + Bachelor's degree with 8 years of ... and maintain an active clearance.** **Roles and Responsibilities:** + Responsible for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding… more
- Northrop Grumman (Jessup, MD)
- … level. Qualifications for both are listed below:** **Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:** + Bachelor's degree ... RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion) + Proficiency with current ASIC design tools for all… more
- Cadence Design Systems, Inc. (Austin, TX)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate ... preferred. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- Northrop Grumman (Linthicum Heights, MD)
- …+ 4 years of experience in the full product life cycle of ASIC Design **Preferred Qualifications:** + Master's Degree in Electrical or Computer Engineering + ... Knowledge of Synthesis, Place & Route (P&R), and Design-for-Test ( DFT ) methodologies + Active DoD Secret Clearance or higher + Effective communication and… more