- DBSI Services, Inc. (Fairfax, CA)
- …maintenance activities. *Complete work assignments required within budget, manpower and timing constraints . *Support plant in achieving Safety, People, Quality, ... to work well with others, exhibiting teamwork skills. *Ability to partner with senior management to analyze and solve issues. *Ability to handle multiple projects… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop ... this role, you'll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy … more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... You will play a critical role in defining cross-domain timing constraints , validating IO timing ...equivalent experience). + 6+ years of experience in static timing analysis, methodology , or constraint development. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... can offer. + Work on various aspects of STA, constraints , timing and power optimization. What We...sign-off + Good knowledge of extraction, device physics, STA methodology and EDA tools limitations. Good understanding of mathematics/physics… more
- NVIDIA (Santa Clara, CA)
- … including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of ... next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our...and power/area/congestions/yield/etc. + Work on all aspects of DFT/Test timing such as timing constraints ,… more
- NVIDIA (Santa Clara, CA)
- …driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints , timing and power convergence, and ... multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology ... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints … more
- NVIDIA (Santa Clara, CA)
- …chip level. + Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints , driving timing and power ... ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology ...in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …and convergence of high-performance designs. + You will be responsible for all aspects of timing including setting up timing constraints , timing analysis ... timing closure of high-speed designs. + Strong background and experience in timing constraints generation, clocking, process variations and signal integrity +… more
- Capgemini (CO)
- **About the Job You're Considering** + Develop block-level and SoC-level timing constraints , and drive full-chip STA setup and signoff for multi-corner, ... failures. **Your Role** + Develop block and SoC timing constraints , and perform full-chip STA setup...methodology , with a strong preference for experience in timing closure of high-performance designs. + Proven expertise in… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. + Contribute to full chip integration and timing methodology /analysis. + Develop and analyze functional coverage. + Help ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San...or System Verilog programming skills + Experience with simulators/synthesis/static timing constraints and related tools (eg, VCS,… more
- Cisco (San Jose, CA)
- …+ Prior DFX experience (DFT + Debug logic/features) + Prior exposure to LINT/CDC/ timing constraints /etc + Verilog design experience - developing custom DFT logic ... Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose,...**Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing … more
- Amazon (Portland, OR)
- …STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip / Sub-System STA and Signoff for a ... latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on...complex, multi-clock, multi-voltage SoC. * Streamlining the timing signoff criterions, timing analysis methodologies and… more
- Bosch (Plymouth, MI)
- …solutions and integrate on automotive platforms work according to agile methodology (scrum), including performing code reviews, design reviews, testing and writing ... hardware engineers, and stakeholders to understand system requirements and constraints . Architect embedded software systems, balancing performance, power consumption,… more
- Citigroup (Getzville, NY)
- Risk Senior Project Manager partners with multiple teams to execute highly transformational, complex risk programs while ensuring the goals & objectives are ... successfully delivered. Expectations include ability to engage senior stakeholders at CAO, CRO and MD level to...Personal Banking Risk and Wealth Risk including definition and timing of work streams, deliverables and other milestones against… more
- Ford Motor Company (Dearborn, MI)
- …workforce and time calculation. + Responsible for defining and managing the technical, timing and budget of multiple projects + Document and track enablers and ... teams to successfully complete projects within time & resource constraints + Track project progress & report effectively on...blockers & changes to customer as well as internal senior management + Track project costs & drive cost… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will ... **Experience in developing and implementing Power-grid and high speed clock constraints and specification.** + **Good understanding of physical design verification … more
