- SpaceX (Sunnyvale, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- SpaceX (Bastrop, TX)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- Meta (Sunnyvale, CA)
- …our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and Hierarchical Clock ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... and I/O interface modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You... analysis . + Own and evolve I/O interface timing signoff , including external interface modeling (eg,… more
- Meta (Sunnyvale, CA)
- …responsible for floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis and signoff 2. Collaborate with RTL design, ... design techniques 11. Proficient in STA, clock tree synthesis and IR drop analysis 12. Knowledge of MBIST, Scan implementation and tradeoffs for physical convergence… more
- Cadence Design Systems, Inc. (Austin, TX)
- … analysis , place and route, extraction, spice etc. Job Responsibilities: + Perform Static timing analysis , glitch, noise analysis , extraction using ... Tempus - Signoff tool. Execute and deliver on timing analysis , ECO flows, Extraction, Power, EMIR...VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge… more
- Cadence Design Systems, Inc. (Austin, TX)
- …innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis , glitch, noise analysis using Tempus ... and customer sites. Requirements; 10+ years of experience in Static timing analysis , Individual should...Tempus - Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to success + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... the netlist-GDS product space focusing on digital implementation and signoff . As an expert Digital Implementation and Signoff...tools including Place and Route, IR Drop, backend design timing and power closure + Experience with advanced nodes… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get involved in design ... SDC Verification + Place and Route + Parasitic Extraction, Timing Signoff , Power Signoff +...Synopsys place and route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis ) + Debug… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …higher) in Computer/Electrical Engineering + Strong knowledge of Digital Design Fundamentals and Static Timing Analysis + Prior experience with IC digital ... implementation flows - Synthesis, Place and Route, IR Drop, Timing Signoff + Prior experience with Cadence tools (Genus, Innovus, Conformal, Tempus, Modus,… more
- Teradyne (North Reading, MA)
- …Understanding in the areas of electromagnetic field and transmission line theory, reflection and static timing analysis , PCB and Package design for power ... models for full Board level Signal and Power Integrity Analysis . Use of 2D and 3D quasi- static ,...simulation of PCB's & packages for signal/power integrity and timing analysis . + Familiarity with IBIS models… more
- Cisco (Maynard, MA)
- …and/or Mentor + Experience with floor planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree ... of input and design collateral. You will work closely with Back-end team on timing signoff for seamless physical design closure. You will work with the… more
- Qualcomm (San Diego, CA)
- …- Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus + Must have good knowledge of static timing analysis , reliability and power analysis + Strong ... + Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff + Hands on experience working with very complex designs that… more
- Qualcomm (San Diego, CA)
- …- Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus + Must have good knowledge of static timing analysis , reliability and power analysis + Strong ... closure + Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff + Hands on experience working with very complex designs that… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …digital design flow from RTL to GDSII including high-level synthesis, RTL synthesis, static timing analysis , power analysis /optimization, equivalence ... checking, DFT, digital implementation, place and route, electrical signoff , and physical signoff . + Must have a proven track-record demonstrating ability to… more
- Qualcomm (San Diego, CA)
- …> GPU ASICS Engineering **General Summary:** **Preferred Qualifications:** + Experience in static timing analysis , constraints and other physical ... using TCL and preferably Perl/Python as well. **Responsibilities** **:** + Timing analysis , validation and debug across multi-mode, multi-voltage domain… more
- Qualcomm (Santa Clara, CA)
- …ability to work effectively within a team environment. + In-depth understanding of extraction, static timing analysis (STA), and electromigration and IR drop ... candidate should have + Proficiency in synthesis, place and route, and signoff timing /power analysis . + Expertise in block-level implementation as well as… more
- Cisco (Portland, OR)
- …- Test Architecture, Methodology and Infrastructure + Background in Test Static Timing Analysis with Test Constraint signoff ownership a plus.. + ... Past experience with Post silicon validation using DFT patterns and product engineering. + Have participated in multiple tapeouts and silicon bringup activities **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect… more